公开(公告)号：US20230245939A1

公开(公告)日：2023-08-03

申请号：US18297927

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L23/16 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/528

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US11594484B2

公开(公告)日：2023-02-28

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US11410953B2

公开(公告)日：2022-08-09

申请号：US16983282

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ho ,  Yi-Wen Wu ,  Chien Ling Hwang ,  Hung-Jui Kuo ,  Chung-Shi Liu

IPC: H01L21/56 ,  H01L27/112 ,  H01L23/31 ,  H01L21/48 ,  H01L21/3105 ,  H01L25/065 ,  H01L27/02 ,  H01L23/00

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

公开(公告)号：US20210375767A1

公开(公告)日：2021-12-02

申请号：US16885291

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ho ,  Hung-Jui Kuo ,  Tzung-Hui Lee

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

公开(公告)号：US11018083B2

公开(公告)日：2021-05-25

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

公开(公告)号：US20210090973A1

公开(公告)日：2021-03-25

申请号：US16698973

申请日：2019-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A structure including a semiconductor die, a conductive pillar, and an insulating encapsulation is provided. The conductive pillar includes a first pillar portion and a second pillar portion disposed on the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. The insulating encapsulation laterally encapsulates the semiconductor die and the conductive pillar.

公开(公告)号：US10930586B2

公开(公告)日：2021-02-23

申请号：US16416278

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/12 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/538 ,  H01L25/10

Abstract: An integrated fan-out package includes a die, an insulating encapsulation, a redistribution circuit structure, conductive terminals, and barrier layers. The insulating encapsulation encapsulates the die. The redistribution circuit structure includes a first redistribution conductive layer on the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, and a second redistribution conductive layer on the first inter-dielectric layer. The first redistribution conductive layer includes conductive through vias extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The first inter-dielectric layer includes contact openings, portions of the second redistribution conductive layer filled in the contact openings are in contact with the first redistribution conductive layer and offset from the conductive through vias. The conductive terminals are disposed over the second surface of the insulating encapsulation. The barrier layers respectively are disposed between the conductive through vias and the conductive terminals.

公开(公告)号：US10861814B2

公开(公告)日：2020-12-08

申请号：US15965981

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Hui Lee ,  Chen-Hua Yu ,  Chi-Ming Tsai ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/683

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a bump structure, a polymer layer and a metal layer. The bump structure includes a metal pad and a bump electrically connected to the metal pad. The polymer layer extends laterally from a sidewall of the bump. The metal layer is over the bump structure and in physical contact with a side surface of the metal pad.

公开(公告)号：US20200328153A1

公开(公告)日：2020-10-15

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

公开(公告)号：US20200294937A1

公开(公告)日：2020-09-17

申请号：US16352838

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Chen ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.