公开(公告)号：US20200227298A1

公开(公告)日：2020-07-16

申请号：US16829248

申请日：2020-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hung Wang ,  Ping-Yin Liu ,  Yeong-Jyh Lin ,  Yeur-Luen Tu

IPC: H01L21/68 ,  G01B11/14 ,  H01L23/544 ,  H01L23/00

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

公开(公告)号：US20190393067A1

公开(公告)日：2019-12-26

申请号：US16015507

申请日：2018-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hung Wang ,  Ping-Yin Liu ,  Yeong-Jyh Lin ,  Yeur-Luen Tu

IPC: H01L21/68 ,  G01B11/14 ,  H01L23/544 ,  H01L23/00

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

公开(公告)号：US20190094682A1

公开(公告)日：2019-03-28

申请号：US16013163

申请日：2018-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

IPC: G03F1/64 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F1/62 ,  G03F7/7015

Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

公开(公告)号：US09834435B1

公开(公告)日：2017-12-05

申请号：US15363389

申请日：2016-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Xin-Hua Huang ,  Yeong-Jyh Lin ,  Jung-Huei Peng

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0058 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/0172 ,  B81C2203/0735

Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a semiconductor substrate including a cavity and a movable feature in the cavity. The semiconductor device structure also includes a cap substrate bonded to the semiconductor substrate to seal the cavity. There is an interface between the cap substrate and the semiconductor substrate. The semiconductor device structure further includes a sealing feature embedded in the semiconductor substrate and surrounding the cavity. The sealing feature extends across the interface and penetrates through the cap substrate.

公开(公告)号：US12255062B2

公开(公告)日：2025-03-18

申请号：US18509053

申请日：2023-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Hsun-Chung Kuang ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: B23K1/00 ,  B23K1/20 ,  B23K20/02 ,  B23K20/233 ,  B23K20/24 ,  H01L21/00 ,  H01L21/02 ,  H01L23/00 ,  B23K101/40 ,  B23K101/42

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

公开(公告)号：US11818944B2

公开(公告)日：2023-11-14

申请号：US16806064

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chia-Shiung Tsai ,  Xin-Hua Huang ,  Yu-Hsing Chang ,  Yeong-Jyh Lin

IPC: H01L51/00 ,  H10K71/16 ,  C23C16/04 ,  C23C16/458 ,  H10K50/125 ,  H10K71/00

CPC classification number: H10K71/166 ,  C23C16/042 ,  C23C16/4584 ,  H10K50/125 ,  H10K71/00

Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

公开(公告)号：US20220208607A1

公开(公告)日：2022-06-30

申请号：US17697557

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/04 ,  H01L25/075 ,  H01L23/538 ,  H01L25/065 ,  H01L23/29 ,  H01L25/00

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

公开(公告)号：US20210272928A1

公开(公告)日：2021-09-02

申请号：US17319558

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: H01L23/00 ,  B23K37/04 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762

Abstract: The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.

公开(公告)号：US20210151353A1

公开(公告)日：2021-05-20

申请号：US17140794

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/04 ,  H01L25/075 ,  H01L23/538 ,  H01L25/065 ,  H01L23/29 ,  H01L25/00

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

公开(公告)号：US20200051950A1

公开(公告)日：2020-02-13

申请号：US16654377

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762 ,  B23K37/04

Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.