公开(公告)号：US11854827B2

公开(公告)日：2023-12-26

申请号：US17364313

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Chun-Hao Kung ,  Tung-Kai Chen ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/321 ,  B24B57/02 ,  B24B37/04 ,  B01F13/08 ,  C09K3/14 ,  B01F33/452

CPC classification number: H01L21/3212 ,  B01F33/452 ,  B24B37/04 ,  B24B57/02 ,  C09K3/1427

Abstract: A chemical-mechanical polishing (CMP) system includes a head, a polishing pad, and a magnetic system. The slurry used in the CMP process contains magnetizable abrasives. Application and control of a magnetic field, by the magnetic system, allows precise control over how the magnetizable abrasives in the slurry may be drawn toward the wafer or toward the polishing pad.

公开(公告)号：US11850704B2

公开(公告)日：2023-12-26

申请号：US17877320

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Yen-Ting Chen ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: B24B53/017 ,  B24B37/20

CPC classification number: B24B53/017 ,  B24B37/20

Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.

公开(公告)号：US20230352554A1

公开(公告)日：2023-11-02

申请号：US18349448

申请日：2023-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L29/66636 ,  H01L21/823475 ,  H01L21/76834 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/41725 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/78 ,  H01L21/823425 ,  H01L29/517

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

公开(公告)号：US20230253474A1

公开(公告)日：2023-08-10

申请号：US18300192

申请日：2023-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/764 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L29/08

CPC classification number: H01L29/4991 ,  H01L29/66636 ,  H01L29/66545 ,  H01L21/764 ,  H01L29/6653 ,  H01L29/6656 ,  H01L21/02164 ,  H01L29/7851 ,  H01L21/31116 ,  H01L21/02167 ,  H01L29/0847 ,  H01L21/0217 ,  H01L29/66795

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

公开(公告)号：US11694933B2

公开(公告)日：2023-07-04

申请号：US16218330

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Yi-Hsiu Liu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.

公开(公告)号：US20210327720A1

公开(公告)日：2021-10-21

申请号：US17364313

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Yen-Ting Chen ,  Chun-Hao Kung ,  Tung-Kai Chen ,  Hui-Chi Huang ,  Kei-Wei Chen

IPC: H01L21/321 ,  C09K3/14 ,  B24B57/02 ,  B24B37/04 ,  B01F13/08

Abstract: A chemical-mechanical polishing (CMP) system includes a head, a polishing pad, and a magnetic system. The slurry used in the CMP process contains magnetizable abrasives. Application and control of a magnetic field, by the magnetic system, allows precise control over how the magnetizable abrasives in the slurry may be drawn toward the wafer or toward the polishing pad.

公开(公告)号：US20210126104A1

公开(公告)日：2021-04-29

申请号：US17121385

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/764 ,  H01L29/08

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

公开(公告)号：US10535525B2

公开(公告)日：2020-01-14

申请号：US15692221

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Chun-Hsiung Lin ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Cheng-Yu Yang ,  Yen-Ting Chen

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/165

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.

公开(公告)号：US10283624B1

公开(公告)日：2019-05-07

申请号：US15875485

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Chi-On Chui ,  Cheng-Yu Yang ,  Yen-Ting Chen ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/762 ,  H01L21/306 ,  H01L29/417

Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

公开(公告)号：US20190067126A1

公开(公告)日：2019-02-28

申请号：US15966186

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L27/092

Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.