公开(公告)号：US20240372008A1

公开(公告)日：2024-11-07

申请号：US18776617

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US20240363626A1

公开(公告)日：2024-10-31

申请号：US18766867

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/7682 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US12125850B2

公开(公告)日：2024-10-22

申请号：US17234256

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/78 ,  H10B12/00 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/785 ,  H10B12/31 ,  H10B12/36 ,  H01L27/0924 ,  H10B12/34 ,  H10B12/37

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US20240312913A1

公开(公告)日：2024-09-19

申请号：US18184085

申请日：2023-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Yi-Hsun Chiu ,  Yu-Xuan Huang

IPC: H01L23/528 ,  H01L21/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L21/7806 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method includes forming a vertical transistor, and the method includes forming a vertical semiconductor bar over a substrate, forming a gate dielectric and a gate electrode encircling the vertical semiconductor bar, forming a first source/drain region over a top surface of the vertical semiconductor bar, removing the substrate to reveal a bottom surface of the vertical semiconductor bar; and forming a second source/drain region contacting the bottom surface of the vertical semiconductor bar. The method further includes forming a backside power line, with the backside power line being on a bottom side of the vertical semiconductor bar. The backside power line is connected to the second source/drain region.

公开(公告)号：US20230369504A1

公开(公告)日：2023-11-16

申请号：US18357357

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L29/78618 ,  H01L23/5286 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66636 ,  H01L29/66742 ,  H01L21/31116 ,  H01L21/02603

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US20230369324A1

公开(公告)日：2023-11-16

申请号：US18358140

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L23/535

CPC classification number: H01L27/0886 ,  H01L21/7682 ,  H01L29/7851 ,  H01L29/42392 ,  H01L29/41791 ,  H01L29/66795 ,  H01L23/535

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US11652043B2

公开(公告)日：2023-05-16

申请号：US17158409

申请日：2021-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Yu-Xuan Huang

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L27/088

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

公开(公告)号：US11532627B2

公开(公告)日：2022-12-20

申请号：US17093230

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Wei Ju Lee ,  Hou-Yu Chen ,  Chun-Fu Cheng

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/538

Abstract: A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.

公开(公告)号：US20220271026A1

公开(公告)日：2022-08-25

申请号：US17181196

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao Yi Hung ,  Yu-Xuan Huang ,  Kuo-Ji Chen

IPC: H01L27/02 ,  H01L23/528

Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.

公开(公告)号：US20220181496A1

公开(公告)日：2022-06-09

申请号：US17682806

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yi-Bo Liao ,  Sai-Hooi Yeong ,  Hou-Yu Chen ,  Yu-Xuan Huang ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/324 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.