公开(公告)号：US20180301453A1

公开(公告)日：2018-10-18

申请号：US16012742

申请日：2018-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Tsan-Chun Wang ,  Kei-Wei Chen

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

公开(公告)号：US10062780B2

公开(公告)日：2018-08-28

申请号：US15652271

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US10008418B2

公开(公告)日：2018-06-26

申请号：US15282981

申请日：2016-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Chia-Ping Lo ,  Liang-Gi Yao ,  Weng Chang ,  Yee-Chia Yeo ,  Ziwei Fang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/324 ,  H01L21/02 ,  H01L21/268

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/268 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

公开(公告)号：US20170256539A1

公开(公告)日：2017-09-07

申请号：US15062210

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Tsan-Chun Wang ,  Kei-Wei Chen

IPC: H01L27/088 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

公开(公告)号：US09508556B1

公开(公告)日：2016-11-29

申请号：US15009828

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen

IPC: H01L29/66 ,  H01L21/30 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01J37/3244 ,  H01J37/32449 ,  H01L21/3065 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/66636 ,  H01L29/785

Abstract: A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes steps as follows. A gate stack is formed over a substrate having a semiconductor fin. Recesses are formed in the semiconductor fin beside the gate stack. A pre-clean process is performed to remove native oxides on surfaces of the recesses. After the pre-clean process, a selectivity proximity push process is performed using a fluorine-containing gas and a first hydrogen gas to the recesses. Strained layers are formed in the recesses.

Abstract translation: 提供了制造鳍式场效应晶体管（FinFET）的方法。 该方法包括以下步骤。 在具有半导体鳍片的衬底上形成栅叠层。 在栅堆叠旁边的半导体鳍形成凹部。 执行预清洁处理以去除凹部表面上的天然氧化物。 在预清洁处理之后，使用含氟气体和第一氢气对凹部进行选择性接近推动过程。 应变层形成在凹部中。

公开(公告)号：US12165912B2

公开(公告)日：2024-12-10

申请号：US18341172

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/51 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having an active region and an isolation region. The semiconductor structure includes gate stacks on the substrate that extend over the active region and the isolation region. The semiconductor structure includes a gate spacer on sidewalls of the gate stacks. The semiconductor structure includes an interlevel dielectric (ILD) layer over the substrate and implanted with one or more dopants, the ILD layer having a top implanted portion over a bottom nonimplanted portion. The top implanted portion seals an air gap between a sidewall of the ILD layer and the gate spacer.

公开(公告)号：US20240258318A1

公开(公告)日：2024-08-01

申请号：US18594073

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

公开(公告)号：US11901450B2

公开(公告)日：2024-02-13

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/0234 ,  H01L21/02181 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20220359283A1

公开(公告)日：2022-11-10

申请号：US17868654

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/768 ,  H01L21/02

Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

公开(公告)号：US20220336262A1

公开(公告)日：2022-10-20

申请号：US17859228

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/266

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate that extends from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; forming a mask layer over the substrate that exposes a portion of the ILD layer and a portion of the outer gate spacer; selectively etching the exposed portion of the outer gate spacer, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.