公开(公告)号：US5267198A

公开(公告)日：1993-11-30

申请号：US953747

申请日：1992-09-29

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US20110314213A1

公开(公告)日：2011-12-22

申请号：US13008189

申请日：2011-01-18

申请人： Kunio UCHIYAMA ,  Osamu Nishii

发明人： Kunio UCHIYAMA ,  Osamu Nishii

IPC分类号： G06F12/00

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

摘要翻译： 一种处理器系统，包括：具有处理器核心和控制器核心的处理器; 以及多个同步存储器芯片，其中所述处理器和所述多个同步存储器芯片经由外部总线连接; 其中所述处理器核心和所述控制器核心经由内部总线连接; 其中所述多个同步存储器芯片根据时钟信号被操作; 其中所述控制器核心包括通过来自所述处理器核心的地址信号选择的模式寄存器，并且通过来自所述处理器核心的数据信号写入信息以选择所述多个同步存储器芯片的操作模式;以及控制单元， 基于写在模式寄存器中的信息，向多个同步存储器芯片操作模式，其中控制器核心基于写入模式寄存器中的信息或从处理器核心到多个存储器芯片的访问地址信号输出模式设置信号 选择性地通过外部总线的同步存储器芯片; 并且其中所述时钟信号被共同地提供给所述多个同步存储器芯片。

公开(公告)号：US20110208983A1

公开(公告)日：2011-08-25

申请号：US13101678

申请日：2011-05-05

申请人： Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

发明人： Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

IPC分类号： G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US07254082B2

公开(公告)日：2007-08-07

申请号：US11363060

申请日：2006-02-28

申请人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

发明人： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC分类号： G11C8/00 ,  G11C5/14

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

摘要： When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

摘要翻译： 相反，当通过电源开关减小不使用状态下的电路块的漏电流时，短时间内开关频繁的接通/断开操作会引起消耗功率的增加。 由于开关的接通需要预热时间，直到电路块变得可用，所以在操作期间的开关的控制使半导体器件的处理时间变差。 该开关通过CPU核心的任务持续时间进行ON / OFF控制，用于将逻辑电路和存储器核心作为一个单元进行控制。 关闭开关后，考虑到预热时间，开关将在任务结束前再次打开。

公开(公告)号：US06604202B1

公开(公告)日：2003-08-05

申请号：US09442148

申请日：1999-11-18

申请人： Osamu Nishii ,  Masayuki Miyazaki ,  Kiyoo Itoh

发明人： Osamu Nishii ,  Masayuki Miyazaki ,  Kiyoo Itoh

IPC分类号： G06F132

CPC分类号： G06F9/3885 ,  G06F9/30145 ,  G06F9/38

摘要： In order to save a sub-threshold leak current during operation of processor, a decision circuit (instruction decoder) inputs an instruction signal and outputs an operation mode signal regarding the level of a leak current based on information about use of the circuit block. Thereby, a sub-threshold leak current in the circuit block not used can be saved.

摘要翻译： 为了在处理器的操作期间保存次阈值泄漏电流，判定电路（指令译码器）根据关于电路块的使用的信息输入指令信号并输出​​关于泄漏电流电平的操作模式信号。 因此，可以节省未使用的电路块中的次阈值泄漏电流。

公开(公告)号：US06334166B1

公开(公告)日：2001-12-25

申请号：US09520834

申请日：2000-03-08

申请人： Kunio Uchiyama ,  Osamu Nishii

发明人： Kunio Uchiyama ,  Osamu Nishii

IPC分类号： G06F1202

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

公开(公告)号：US5740401A

公开(公告)日：1998-04-14

申请号：US9077

申请日：1993-01-26

申请人： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

发明人： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F12/08 ,  G06F12/14 ,  G06F15/177

CPC分类号： G06F9/52 ,  G06F12/0806 ,  G06F12/1466

摘要： A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.

摘要翻译： 多处理器系统包括地址总线170，数据总线180，处理器110和120，访问队列135和145，共享存储器130和140以及锁定控制电路500和510.特别地，锁定指示标志寄存器501是 当一个处理器110中的操作数高速缓存112正在对共享存储器130的预定地址进行锁定访问时，标志寄存器501是基于锁定命令信号260设置的， 在另一个处理器120中的指令高速缓存122到共享存储器130的预定地址的访问是被禁止的，但是在锁定访问时允许访问不同的地址。 在锁定访问被释放之后，锁定控制电路500接受对预定地址的访问。

公开(公告)号：US5652858A

公开(公告)日：1997-07-29

申请号：US455335

申请日：1995-05-31

申请人： Tetsuhiko Okada ,  Osamu Nishii ,  Hiroshi Takeda

发明人： Tetsuhiko Okada ,  Osamu Nishii ,  Hiroshi Takeda

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/30043 ,  G06F12/0862 ,  G06F9/383 ,  G06F2212/1024 ,  G06F2212/6022 ,  G06F2212/6028

摘要： In order to allow prefetching of pointer-type data structure, an instruction word of load instruction has pointer hints indicating that the data being loaded by the instruction comprises a pointer specifying the address of the next data. When a CPU executes such an instruction, and the data requested by that instruction is loaded from a main memory, a prefetch circuit in a memory interface circuit uses this pointer to read a block containing the data specified by this pointer from the main memory, then stores temporarily in a prefetch buffer provided therein. When CPU executes a load instruction requesting reading of the data specified by this pointer, the data in this stored block is supplied to CPU through a processor interface circuit and a cache control circuit.

摘要翻译： 为了允许指针型数据结构的预取，加载指令的指令字具有指示符提示，指示由指令加载的数据包括指定下一个数据的地址的指针。 当CPU执行这样的指令，并且从主存储器加载由该指令请求的数据时，存储器接口电路中的预取电路使用该指针从主存储器读取包含由该指针指定的数据的块，然后 临时存储在其中提供的预取缓冲器中。 当CPU执行请求读取由该指针指定的数据的加载指令时，该存储块中的数据通过处理器接口电路和高速缓存控制电路提供给CPU。

公开(公告)号：US5574876A

公开(公告)日：1996-11-12

申请号：US118191

申请日：1993-09-09

申请人： Kunio Uchiyama ,  Osamu Nishii

发明人： Kunio Uchiyama ,  Osamu Nishii

IPC分类号： G06F15/78 ,  G11C7/10 ,  G11C8/12 ,  G11C8/18 ,  H04N7/26 ,  H04N7/50 ,  G06F12/06

CPC分类号： G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

摘要： A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a node register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

摘要翻译： 主存储装置是具有多个存储体和用于确定操作模式的节点寄存器的同步动态存储器，主存储控制器耦合到处理器和主存储装置，以及用于实现对并行访问的控制的装置 在主存储控制器中布置有多个存储器组以及将操作模式设置到内置寄存器的控制。 因此，可以确保使用高通用性和常规存储器的常规处理器。

公开(公告)号：US5193075A

公开(公告)日：1993-03-09

申请号：US490745

申请日：1990-03-08

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。