公开(公告)号：US5252868A

公开(公告)日：1993-10-12

申请号：US764512

申请日：1991-09-20

Applicant: Takashi Miida ,  Tatsuya Hagiwara ,  Yasumasa Hasegawa

Inventor： Takashi Miida ,  Tatsuya Hagiwara ,  Yasumasa Hasegawa

IPC: H01L27/092 ,  G11C27/04 ,  H01L21/339 ,  H01L21/8238 ,  H01L29/762 ,  H03K5/02 ,  H03K5/13 ,  H03K5/153

CPC classification number: G11C27/04 ,  H03K5/023 ,  H03K5/133

Abstract: A CCD amplifier circuit including an active load type source-grounded inverting amplifier circuit which includes a driving MOS transistor, an active load MOS transistor connected to the driving MOS transistor, and a control circuit. The control circuit controls the voltage at the gate electrode of the active load MOS transistor with a control signal of low output impedance which is substantially inversely proportional to the drain-source voltage of the active load MOS transistor and level-shifted by a predetermined voltage. Further, a CCD delay line includes a floating diffusion region of predetermined impurities formed at an end of a charge-coupled device with a gate section having a predetermined fixed gate voltage, and a switched capacitor integrator for detecting the injection charge of the floating diffusion region to detect signal charges transferred to the floating diffusion region from the charge-coupled device. The CCD amplifier circuit is employed as an output circuit of the switched capacitor integrator.

Abstract translation: 一种CCD放大器电路，包括有源负载型源极接地反相放大器电路，其包括驱动MOS晶体管，连接到驱动MOS晶体管的有源负载MOS晶体管和控制电路。 控制电路利用与有源负载MOS晶体管的漏极 - 源极电压基本上成反比且电平移动预定电压的低输出阻抗的控制信号来控制有源负载MOS晶体管的栅电极处的电压。 此外，CCD延迟线包括形成在具有预定的固定栅极电压的栅极部分的电荷耦合器件的端部处的预定杂质的浮动扩散区域和用于检测浮动扩散区域的注入电荷的开关电容积分器 以检测从电荷耦合器件转移到浮动扩散区的信号电荷。 CCD放大器电路用作开关电容积分器的输出电路。

公开(公告)号：US4945377A

公开(公告)日：1990-07-31

申请号：US216360

申请日：1988-07-07

Applicant: Takashi Miida ,  Nozomu Ozaki

Inventor： Takashi Miida ,  Nozomu Ozaki

IPC: G01C3/06 ,  G01C3/00 ,  G02B7/34 ,  G03B13/36

CPC classification number: G02B7/34

Abstract: A phase difference-detecting apparatus for detecting a relative distance between a pair of focused images obtained from a subject luminous flux passed through an objective lens to thereby judge a focusing state of the objective lens. The apparatus includes a pair of signal generating sections which receive the subject flux and provide first and second time series signals. A switching-capacitor integrator is provided including a plurality of capacitive elements and switching elements for intermittently connecting the capacitive elements to each other, and for receiving the first and second time series signals. A control device compares the sizes of the first and second time series signals with each other to thereby generate a control signal corresponding to a relation of size between the first and second time series signals. The switching elements are controlled on the basis of the control signal to cause the switching-capacitor integrator to generate an electric charge corresponding to an integrated value of an absolute value of a difference between the first and second time series signals, and to cause the switching-capacitor integrator to generate, as a correlation value, an integrated value on the basis of the first and second time series signals in predetermined numbers whenever the quantity of relative movement is changed. The switching-capacitor integrator includes a gain control including a plurality of switchable capacitances.

Abstract translation: 一种相位差检测装置，用于检测从通过物镜的目标光束获得的一对聚焦图像之间的相对距离，从而判断物镜的聚焦状态。 该装置包括一对信号产生部分，其接收对象通量并提供第一和第二时间序列信号。 提供一种开关电容积分器，其包括多个电容元件和用于间歇地将电容元件彼此连接的开关元件，以及用于接收第一和第二时间序列信号。 控制装置将第一和第二时间序列信号的大小彼此进行比较，从而产生对应于第一和第二时间序列信号之间的大小关系的控制信号。 基于控制信号控制开关元件，使开关电容积分器产生与第一和第二时间序列信号之间的差的绝对值的积分值相对应的电荷，并使开关元件 电容积分器，每当相对移动量发生变化时，根据第一和第二时间序列信号，以相关值生成预定数量的积分值。 开关电容积分器包括包括多个可切换电容的增益控制。

公开(公告)号：US4750042A

公开(公告)日：1988-06-07

申请号：US2330

申请日：1987-01-12

Applicant: Jin Murayama ,  Takashi Miida

Inventor： Jin Murayama ,  Takashi Miida

IPC: H01L27/148 ,  G11C27/04 ,  H01L27/14 ,  H04N5/335 ,  H04N5/341 ,  H04N5/372 ,  H04N3/14

CPC classification number: G11C27/04 ,  H04N3/1575

Abstract: A horizontal transfer section for a solid state image-pickup matrix, in which the parallel signals are first read by a first horizontal CCD. A second horizontal CCD is aligned in parallel with the first one and having a deeper potential well. A gate electrode separates the two CCDs. Thereby, the gate electrode can transfer charges from the first to the second CCD and the first CCD can be refilled with different signals. The two horizontal CCDs can be serially read out by common clocking signals.

Abstract translation: 用于固态摄像矩阵的水平传送部分，其中并行信号首先由第一水平CCD读取。 第二个水平CCD与第一个水平CCD平行排列并具有较深的势阱。 栅电极分离两个CCD。 由此，栅电极可以从第一CCD传输电荷到第二CCD，并且可以用不同的信号重新填充第一CCD。 两个水平CCD可以通过公共时钟信号串行读出。

公开(公告)号：US4672409A

公开(公告)日：1987-06-09

申请号：US746452

申请日：1985-06-19

Applicant: Akira Takei ,  Yoshihiko Hika ,  Takashi Miida

Inventor： Akira Takei ,  Yoshihiko Hika ,  Takashi Miida

IPC: H01L21/8239 ,  H01L29/788 ,  H01L29/861 ,  H01L29/78 ,  G11C11/40 ,  H01L29/04 ,  H01L29/34

CPC classification number: H01L27/1052 ,  H01L29/7883 ,  H01L29/8616

Abstract: A nonvolatile semiconductor memory device including at least one memory cell which comprises a floating-gate, a control gate and a single impurity diffusion region formed exclusively for the memory cell. In this device, a small depletion region and a large depletion region due to the charged and discharged state of the floating-gate represent the information "1" and "0".

Abstract translation: 一种非易失性半导体存储器件，包括至少一个存储单元，该存储单元包括浮置栅极，控制栅极和专门为存储单元形成的单个杂质扩散区域。 在该装置中，由于浮置栅极的充放电状态而导致的小的耗尽区域和大的耗尽区域表示信息“1”和“0”。

公开(公告)号：US07256443B2

公开(公告)日：2007-08-14

申请号：US11053952

申请日：2005-02-10

Applicant: Takashi Miida

Inventor： Takashi Miida

IPC: H01L29/76

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L29/7887

Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

Abstract translation: 半导体存储器具有以矩阵排列的多个单元晶体管。 单元晶体管包括硅衬底，控制栅极，一对电隔离的浮动栅极。 在P型硅衬底中形成多个突起，并且在突起的两侧形成作为源极和漏极的一对N型扩散区域。 控制门通过第四绝缘层面向突出部。 浮动栅极的侧表面经由第一绝缘层面对突起的侧表面，并且经由第三绝缘层面对控制栅极。 浮栅经由第一绝缘层面向扩散区。

公开(公告)号：US07221029B2

公开(公告)日：2007-05-22

申请号：US11236629

申请日：2005-09-28

Applicant: Takashi Miida

Inventor： Takashi Miida

IPC: H01L29/76

CPC classification number: H01L27/11521 ,  H01L27/105 ,  H01L27/11524 ,  H01L27/11553 ,  H01L29/7887

Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

Abstract translation: 单元晶体管包括形成在比其沟道区的一部分更低的电平的源/漏区。 选择晶体管具有形成在与单元晶体管的源极/漏极区域基本相同的电平的沟道区域和源极/漏极区域。 单元晶体管的源极/漏极区域之一和选择晶体管的源极/漏极区域中的一个在基本上相同的平面中彼此电互连。

公开(公告)号：US20060027857A1

公开(公告)日：2006-02-09

申请号：US11236629

申请日：2005-09-28

Applicant: Takashi Miida

Inventor： Takashi Miida

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/105 ,  H01L27/11524 ,  H01L27/11553 ,  H01L29/7887

Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

公开(公告)号：US06937525B2

公开(公告)日：2005-08-30

申请号：US10300027

申请日：2002-11-20

Applicant: Takashi Miida

Inventor： Takashi Miida

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7887

Abstract: A multiple-bit transistor includes P type semiconductor including a projection, a gate insulation layer, a pair of N type source/drain regions, tunnel insulation layers, a pair of floating gates, inter-polycrystalline insulation layers, and a control gate. The root portion of the projection, which is defined by a straight line virtually connecting the source/drain regions, is higher in the concentration of the P type impurity than the other portion. A potential difference for write-in is set up between the source/drain regions while a write voltage is applied to the control gate, thereby causing electrons to be ballistically injected into at least one of the floating gates.

Abstract translation: 多位晶体管包括P型半导体，其包括突起，栅极绝缘层，一对N型源极/漏极区，隧道绝缘层，一对浮动栅极，多晶硅绝缘层和控制栅极。 由虚拟连接源极/漏极区域的直线限定的突起的根部比P型杂质的浓度高于其他部分。 在写入电压施加到控制栅极之间，在源极/漏极区域之间建立用于写入的电位差，从而使电子被弹道地注入至少一个浮动栅极。

公开(公告)号：US06653164B2

公开(公告)日：2003-11-25

申请号：US10290363

申请日：2002-11-08

Applicant: Takashi Miida

Inventor： Takashi Miida

IPC: H01L2100

CPC classification number: H01L27/14609 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14687

Abstract: A sole state imaging device includes a photodetection diode and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In a method of making the device, a carrier pocket is formed in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Abstract translation: 单独状态成像装置包括与用于光信号检测的光电二极管相邻设置的光电二极管和绝缘栅场效应晶体管。 在制造该器件的方法中，在第二阱区域中形成载流子袋，并且形成元件隔离绝缘膜以隔离相邻的单位像素。 此外，形成相反导电类型的元件隔离区以隔离一个导电类型的第二半导体层，以便包括元件隔离绝缘膜的下表面并到达第一半导体层。

公开(公告)号：US06545331B1

公开(公告)日：2003-04-08

申请号：US09722041

申请日：2000-11-27

Applicant: Takashi Miida

Inventor： Takashi Miida

IPC: H01L3100

CPC classification number: H01L27/14609 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14687

Abstract: Disclosed is a solid state imaging device, comprising: a photodetection diode; and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In this case, a carrier pocket is provided in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Abstract translation: 公开了一种固态成像装置，包括：光电检测二极管; 以及与用于光信号检测的光检测二极管相邻设置的绝缘栅场效应晶体管。 在这种情况下，在第二阱区域中设置载流子袋，并且形成元件隔离绝缘膜以隔离相邻的单位像素。 此外，形成相反导电类型的元件隔离区以隔离一个导电类型的第二半导体层，以便包括元件隔离绝缘膜的下表面并到达第一半导体层。