公开(公告)号：US20210020453A1

公开(公告)日：2021-01-21

申请号：US16784619

申请日：2020-02-07

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Jodi GRZESKOWIAK ,  Anton J. DEVILLIERS

IPC: H01L21/321 ,  H01L21/768

Abstract: The disclosure relates to techniques and methods for planarizing a substrate by amplifying and controlling z-height technology. Variability of z-height can be modeled or measured for each device. A counter height pattern can then be created and processed on a substrate. By using different materials with different etch rates, a planarizing pattern can be transferred to the substrate or system to create a planarized substrate surface for improved lithography. Additionally, a transition region slope can be precisely controlled using the same methods.

公开(公告)号：US20180374791A1

公开(公告)日：2018-12-27

申请号：US16011377

申请日：2018-06-18

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Anton J. DEVILLIERS ,  Kandabara TAPILY

IPC: H01L23/528 ,  H01L29/06 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768

Abstract: Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric cap that isolates the power rail from conductive pattern structures on the dielectric cap. Further, an opening is selectively formed in the dielectric cap and is filled with conductive material to selectively connect a conductive pattern structure with the power rail.

公开(公告)号：US20230326767A1

公开(公告)日：2023-10-12

申请号：US17885097

申请日：2022-08-10

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Andrew WELOTH ,  David C. CONKLIN ,  Anton J. DEVILLIERS

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/67 ,  H01L23/31 ,  H01L21/66

CPC classification number: H01L21/56 ,  H01L24/80 ,  H01L21/67225 ,  H01L21/67109 ,  H01L21/67092 ,  H01L23/3171 ,  H01L22/20 ,  H01L2224/80007 ,  H01L2224/80013 ,  H01L2224/80011 ,  H01L2224/08145 ,  H01L24/08 ,  H01L23/291

Abstract: A method, for bonding a first wafer to a second wafer, includes generating a first modification map based on wafer shape data of the first wafer and the second wafer. The first modification map defines adjustments to internal stresses of the first wafer. A first wafer shape of the first wafer is modified by forming a first stressor film on the first wafer based on the first modification map. The first wafer is aligned with the second wafer after the modifying. The first wafer is bonded to the second wafer.

公开(公告)号：US20230161267A1

公开(公告)日：2023-05-25

申请号：US17888553

申请日：2022-08-16

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  Anton J. DEVILLIERS ,  H. Jim FULFORD

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70625

Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

公开(公告)号：US20220350246A1

公开(公告)日：2022-11-03

申请号：US17735726

申请日：2022-05-03

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS

IPC: G03F7/09 ,  H01L21/311 ,  H01L21/027

Abstract: A method of patterning a substrate includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a first layer of a wet photoresist deposited by spin-on deposition, and a second layer of a dry photoresist deposited by vapor deposition. The first layer is positioned over the second layer. A first relief pattern is formed in the first layer by exposure to a first pattern of actinic radiation of a first wavelength and development of developable portions of the first layer using a first development process. The first relief pattern uncovers portions of the second layer. A multi-color layer of the first relief pattern is formed. The multi-color layer includes the wet photoresist and a third material that is different from the wet photoresist and the dry photoresist. A selective patterning process is executed for uncovered portions of one or two of the wet photoresist, the dry photoresist and the third material.

公开(公告)号：US20210366713A1

公开(公告)日：2021-11-25

申请号：US17325425

申请日：2021-05-20

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Anton J. DEVILLIERS

IPC: H01L21/033 ,  H01L21/027

Abstract: Devices are made by self-aligned quad pitch patterning (SAQP), staircase patterning and double staircase patterning. Methods for making devices by self-aligned quad pitch patterning (SAQP) use a single spacer in the process. Methods for making devices by staircase patterning and double staircase patterning do not use a spacer. An intermediate process step called self-aligned double patterning (SADP) is used to double the pitch following the spacer deposition. A pattern is formed on a substrate, the pattern having ultra-fine resolutions by repeating the SADP step twice for pitch quadrupling and introducing a reversal layer to form a fine trench pattern and hole pattern. The pattern designs or pattern layouts have improved LER/LWR (line edge roughness and line width roughness respectively) for below 12 nm lines and trenches in order to create self-aligned cross pitch quad trenches.

公开(公告)号：US20210339276A1

公开(公告)日：2021-11-04

申请号：US17196189

申请日：2021-03-09

Applicant: Tokyo Electron Limited

Inventor： Mirko VUKOVIC ,  Daniel FULFORD ,  Anton J. DEVILLIERS

IPC: B05B12/08 ,  G01B11/06

Abstract: Light can be used to monitor coating a liquid on a substrate. By directing the light to a spot on the substrate, when the liquid passes through the spot, some light will be reflected, while some light will be scattered. Monitoring this behavior can indicate whether a substrate has been successfully coated with the liquid, as well as identifying defects. Further, coating times can be monitored to make process adjustments.

公开(公告)号：US20210202481A1

公开(公告)日：2021-07-01

申请号：US17136820

申请日：2020-12-29

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Anton J. DEVILLIERS ,  Mark I. GARDNER ,  Daniel CHANEMOUGAME ,  Jeffrey SMITH ,  Lars LIEBMANN ,  Subhadeep KAL

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

公开(公告)号：US20210175327A1

公开(公告)日：2021-06-10

申请号：US16848738

申请日：2020-04-14

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Anton J. DEVILLIERS

IPC: H01L29/06 ,  H01L21/822 ,  H01L21/8239 ,  H01L21/02

Abstract: Transistor/semiconductor devices and methods of forming transistor/semiconductor devices. The devices include a metal layer with dielectric isolation within existing 3D silicon stacks. Two different disposable materials within the 3D silicon stack are selectively removed later from other layers in the stack to become future metal layers and oxide layer respectively, to provide the metal line isolated in a vertical central portion of the stack.

公开(公告)号：US20210013111A1

公开(公告)日：2021-01-14

申请号：US16924937

申请日：2020-07-09

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Kandabara TAPILY ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Mark GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.