公开(公告)号：US20170194212A1

公开(公告)日：2017-07-06

申请号：US15008462

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ying-Cheng Liu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Chih-Sen Huang

IPC: H01L21/8238 ,  H01L29/161 ,  H01L27/092 ,  H01L29/24 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L21/823814 ,  H01L21/823425 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first fin-shaped structure and a second fin-shaped structure on the substrate; forming a first epitaxial layer on the first fin-shaped structure and a second epitaxial layer on the second fin-shaped structure; and forming a cap layer on the first epitaxial layer and the second epitaxial layer. Preferably, a distance between the first epitaxial layer and the second epitaxial layer is between twice the thickness of the cap layer and four times the thickness of the cap layer.

公开(公告)号：US20170098707A1

公开(公告)日：2017-04-06

申请号：US14932993

申请日：2015-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yi-Kuan Wu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/31 ,  H01L27/088 ,  H01L21/285 ,  H01L29/26 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/088 ,  H01L21/02521 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66969

Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.

公开(公告)号：US09548239B2

公开(公告)日：2017-01-17

申请号：US14612235

申请日：2015-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract translation: 首先在衬底上形成栅极结构，并且在栅极结构周围形成层间电介质（ILD）层，在ILD层和栅极结构上形成介电层，在介电层和ILD层中形成开口 并且在介质层和开口中形成有机电介质层（ODL）。 在去除部分ODL后，部分电介质层延伸开口，然后剩余的ODL，在开口处形成接触塞。

公开(公告)号：US09412745B1

公开(公告)日：2016-08-09

申请号：US14620212

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L27/32 ,  H01L27/11 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L27/3223 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.

Abstract translation: 提供一种半导体结构，包括基板，多个第一半导体器件，多个第二半导体器件和多个虚拟插槽触点。 衬底具有器件区域，其中器件区域包括第一功能区域和第二功能区域，并且虚设区域设置在其间。 第一半导体器件和多个第一时隙触点设置在第一功能区域中。 第二半导体器件和多个第二槽触点设置在第二功能区域中。 虚拟插槽触点设置在虚拟区域中。

公开(公告)号：US20160013104A1

公开(公告)日：2016-01-14

申请号：US14455939

申请日：2014-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/768 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/665 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。

公开(公告)号：US09230816B1

公开(公告)日：2016-01-05

申请号：US14629502

申请日：2015-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/324 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3205

CPC classification number: H01L21/28518 ,  H01L21/28052 ,  H01L21/3081 ,  H01L21/32053 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the gate structure and the ILD layer; forming a patterned hard mask on the dielectric layer; forming an opening in the dielectric layer and the ILD layer; performing a silicide process for forming a silicide layer in the opening; removing the patterned hard mask and un-reacted metal after the silicide process; and forming a contact plug in the opening.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成介电层; 在介电层上形成图案化的硬掩模; 在介电层和ILD层中形成开口; 执行在开口中形成硅化物层的硅化物工艺; 在硅化物处理后去除图案化的硬掩模和未反应的金属; 并在开口中形成接触塞。

公开(公告)号：US20150097248A1

公开(公告)日：2015-04-09

申请号：US14549559

申请日：2014-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Abstract translation: 半导体结构包括在基板中的多个第一绝缘体，围绕所述基板中的所述第一绝缘体的侧壁和底部的公共绝缘层，以及在所述公共绝缘层上的所述基板的悬置部分。

公开(公告)号：US12190926B2

公开(公告)日：2025-01-07

申请号：US18108025

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

公开(公告)号：US20240365677A1

公开(公告)日：2024-10-31

申请号：US18329588

申请日：2023-06-06

Applicant: United Microelectronics Corp.

Inventor： Jia-Rong Wu ,  Yi-An Shih ,  Hsiu-Hao Hu ,  I-Fan Chang ,  Rai-Min Huang ,  Po Kai Hsu

IPC: H10N50/20 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/20 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80

Abstract: Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.

公开(公告)号：US12052932B2

公开(公告)日：2024-07-30

申请号：US18132989

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.