公开(公告)号：US20140322883A1

公开(公告)日：2014-10-30

申请号：US14331229

申请日：2014-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Te Wei ,  Wen-Chen Wu ,  Lung-En Kuo ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66689 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Abstract translation: 公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成硅层; 在硅层上进行第一光蚀刻工艺以形成栅极图案; 在与栅极图案的两侧相邻的半导体衬底中形成外延层; 以及对所述栅极图案执行第二光蚀刻处理以在所述栅极图案中形成槽，同时使用所述栅极图案将所述栅极图案物理分离成两个栅极。

公开(公告)号：US20140308761A1

公开(公告)日：2014-10-16

申请号：US13862484

申请日：2013-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/308 ,  H01L21/66

CPC classification number: H01L21/3086 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823821 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26 ,  H01L29/66795 ,  H01L29/785

Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.

Abstract translation: 提供侧壁图像传送（SIT）处理。 首先，提供基板。 在衬底上形成具有图案的牺牲层。 执行第一测量步骤以测量牺牲层的图案的宽度。 材料层在牺牲层上共形地形成，其中根据第一测量步骤的结果调整材料层的厚度。 然后，各向异性地去除材料层，因此材料层成为牺牲层的侧壁上的间隔物。 最后，去除牺牲层。

公开(公告)号：US20140306272A1

公开(公告)日：2014-10-16

申请号：US13863393

申请日：2013-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/762 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。

公开(公告)号：US20130059441A1

公开(公告)日：2013-03-07

申请号：US13666980

申请日：2012-11-02

Applicant: United Microelectronics Corp.

Inventor： Lung-En Kuo

IPC: H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/28123

Abstract: A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.

Abstract translation: 公开了一种制造半导体结构的方法。 该方法包括以下步骤：提供衬底; 在衬底上沉积材料层; 在所述材料层上形成至少一个电介质层; 在介电层上形成图案化的抗蚀剂; 对至少所述图案化抗蚀剂进行第一修整处理; 以及对至少所述电介质层进行第二修整处理，其中所述第二修整工艺包括修剪大于总修整值的70％。

公开(公告)号：US20240006525A1

公开(公告)日：2024-01-04

申请号：US17870746

申请日：2022-07-21

Applicant: United Microelectronics Corp.

Inventor： Yuan Yu Chung ,  Bo-Yu Chen ,  You-Jia Chang ,  Lung-En Kuo ,  Kun-Yuan Liao ,  Chun-Lung Chen

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for manufacturing a high electron mobility transistor device includes providing a substrate. A channel material, a barrier material, a polarization adjustment material and a conductive material are formed on the substrate. A hard mask layer is formed on the conductive material. The conductive material is patterned to form a conductive layer by using the hard mask layer as a mask. A plurality of protection layers is formed on sidewalls of the hard mask layer and the conductive layer. The polarization adjustment material is patterned to form a polarization adjustment layer by using the plurality of protection layers and the hard mask as masks. The plurality of protection layers is removed. A portion of the conductive layer is laterally removed to form a first gate conductive layer.

公开(公告)号：US10164052B2

公开(公告)日：2018-12-25

申请号：US15667629

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

公开(公告)号：US20170330954A1

公开(公告)日：2017-11-16

申请号：US15667629

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

公开(公告)号：US09761690B2

公开(公告)日：2017-09-12

申请号：US14324092

申请日：2014-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

公开(公告)号：US20150206759A1

公开(公告)日：2015-07-23

申请号：US14159457

申请日：2014-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Lung-En Kuo ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.

Abstract translation: 本发明提供一种半导体结构，其包括基板，至少一个翅片组和设置在基板上的多个亚翅片结构，其中，翅片组设置在两个子鳍结构之间，并且每个子鳍结构的顶表面， 翅片结构低于翅片组的顶面; 以及设置在衬底中的浅沟槽隔离（STI），其中子鳍结构被浅沟槽隔离完全覆盖。

公开(公告)号：US09013024B2

公开(公告)日：2015-04-21

申请号：US14054811

申请日：2013-10-15

Applicant: United Microelectronics Corp.

Inventor： Ying-Chih Lin ,  Hsuan-Hsu Chen ,  Jiunn-Hsiung Liao ,  Lung-En Kuo

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/311 ,  H01L21/3083 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Abstract translation: 半导体结构包括基板，凹部和材料。 凹部位于基板中，其中凹部具有上部和下部。 上部的最小宽度大于下部的最大宽度。 材料位于凹槽中。