公开(公告)号：US20180294335A1

公开(公告)日：2018-10-11

申请号：US15623371

申请日：2017-06-14

Applicant: University of Electronic Science and Technology of China

Inventor： Xiaorong LUO ,  Fu PENG ,  Chao YANG ,  Jie WEI ,  Siyu DENG ,  Dongfa OUYANG ,  Bo ZHANG

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/207 ,  H01L29/423 ,  H01L29/78 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/0615 ,  H01L29/1054 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/7788 ,  H01L29/7827

Abstract: The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode HEMT device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient Al composition sequentially on the buffer layer. The gradient trends of the two layers are opposite. The three-dimensional electron gas (3DEG) and the three-dimensional hole gas (3DHG) are induced and generated in the barrier layers due to the inner polarization difference respectively. A trench insulated gate structure is at one side of the source which is away from the metal drain and is in contact with the source. First, since the highly concentrated electrons exist in the entire first barrier layer, the on-state current is improved greatly. Second, the vertical conductive channel between the source and the 3DEG are pinched off by the 3DHG, so as to realize the enhancement mode.

公开(公告)号：US20180026129A1

公开(公告)日：2018-01-25

申请号：US15602122

申请日：2017-05-23

Applicant: University of Electronic Science and Technology of China

Inventor： Min REN ,  Chi XIE ,  Jiaju LI ,  Ziqi ZHONG ,  Zehong LI ,  Jinping ZHANG ,  Wei GAO ,  Bo ZHANG

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7811 ,  H01L21/30604 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/0684 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/407 ,  H01L29/41741

Abstract: Edge termination structures for power semiconductor devices (or power devices) are disclosed. The purpose of this invention is to reduce the difficulty of deep trench etching and dielectric filling by adopting an inverted trapezoidal trench. In order to save the area of edge termination and get a high blocking voltage on condition that the angle between the sidewall of the trench and horizontal is large, fixed charges are introduced at a particular location in the trench. Due to the Coulomb interaction between the ionized impurity in the drift region and the fixed charges, the depletion region of the terminal PN junction can extend fully, which relieves the concentration of electric field there. Therefore, the edge termination can exhibit a high breakdown voltage near to that of the parallel plane junction with a smaller area and the reduced technical difficulty of deep trench etching and dielectric filling.

公开(公告)号：US20250081553A1

公开(公告)日：2025-03-06

申请号：US18388870

申请日：2023-11-13

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Jue LI ,  Zesheng SHI ,  Daoming SHEN ,  Bo ZHANG

IPC: H01L29/06

Abstract: A power semiconductor device, including a cell region, a transition region, and a terminal region. The transition region is located between the cell region and the terminal region of the device. A first conduction type substrate, a first conduction type epitaxial layer located above the first conduction type substrate, and a first conduction type buffer layer located in the first conduction type epitaxial layer are jointly arranged at the bottoms of the cell region, the transition region, and the terminal region of the device. In a high-current application, since the cell region occupies the largest area of a chip, in a case that breakdown can occur in the cell region and the current can be discharged through the cell region. On the basis of ensuring the BV of the terminal region, a silicon layer step is formed by elevating the position of a top structure of the terminal region.

公开(公告)号：US20240395930A1

公开(公告)日：2024-11-28

申请号：US18382561

申请日：2023-10-23

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Yue GAO ,  Jiawei WANG ,  Dingxiang MA ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

公开(公告)号：US20230326973A1

公开(公告)日：2023-10-12

申请号：US17848422

申请日：2022-06-24

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun ZHOU ,  Jianwen CAO ,  Yue SHI ,  Bo ZHANG

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L29/7821 ,  H01L29/66068 ,  H01L29/0619 ,  H01L29/782

Abstract: A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

公开(公告)号：US20230090883A1

公开(公告)日：2023-03-23

申请号：US17752891

申请日：2022-05-25

Applicant: University of Electronic Science and Technology of China

Inventor： Jinping ZHANG ,  Rongrong ZHU ,  Yuanyuan TU ,  Zehong LI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

公开(公告)号：US20230088637A1

公开(公告)日：2023-03-23

申请号：US17752889

申请日：2022-05-25

Applicant: University of Electronic Science and Technology of China

Inventor： Jinping ZHANG ,  Yuanyuan TU ,  Rongrong ZHU ,  Zehong LI ,  Bo ZHANG

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/761 ,  H01L21/765 ,  H01L29/66

Abstract: A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.

公开(公告)号：US20210305051A1

公开(公告)日：2021-09-30

申请号：US17004031

申请日：2020-08-27

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Shida DONG ,  Zhengkang WANG ,  Dong FANG ,  Zhuo WANG ,  Bo ZHANG

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/765 ,  H01L29/66

Abstract: A metal wiring method for reducing gate resistance of a narrow control gate structure, wherein the gate structure is etched with first gate electrodes and second gate electrodes at regular intervals and kept with complete gate electrodes at regular intervals, thereby constituting a structure in which the first and second gate electrodes and the complete gate electrodes are spaced apart. A first contact hole is etched on the complete gate electrode to draw out metal as a first metal layer. A second contact hole is etched on a source region and a split gate to draw out metal as a second metal layer. These two metal layers are separated by a dielectric layer. A multi-point contact of the first layer of metal with the gate electrode in a Y direction reduces the gate resistance caused by an excessively long path in the Y direction of a control gate electrode.

公开(公告)号：US20180164842A1

公开(公告)日：2018-06-14

申请号：US15599484

申请日：2017-05-19

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun ZHOU ,  Yao WANG ,  Jianwen CAO ,  Hongming YU ,  Yunkun WANG ,  Anqi WANG ,  Zhuo WANG ,  Bo ZHANG

IPC: G05F1/46 ,  G05F3/24 ,  G05F3/16 ,  H02J7/00

CPC classification number: G05F1/46 ,  G05F3/16 ,  G05F3/242 ,  H02J7/0047 ,  H02J2007/0095

Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to μT2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of −40° C.˜ 100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from μW level to nW level and realize low power consumption.

公开(公告)号：US20180157283A1

公开(公告)日：2018-06-07

申请号：US15690290

申请日：2017-08-30

Applicant: University of Electronic Science and Technology of China

Inventor： Xin MING ,  Di GAO ,  Jiahao ZHANG ,  Xuan ZHANG ,  Xiuling WEI ,  Yao WANG ,  Zhuo WANG ,  Bo ZHANG

IPC: G05F1/575 ,  H03F3/45

CPC classification number: G05F1/575 ,  H03F3/4521 ,  H03F2203/45288

Abstract: A low-dropout regulator with super transconductance structure relates to the field of power management technology. The super-transconductance structure refers to the circuit structure in which the voltage signal is converted into a current signal and amplified with a high magnification. The error amplifier EA in the present invention uses the super transconductance structure. The differential input pair of the error amplifier EA samples the difference between the feedback voltage VFB and the dynamic reference voltage VREF1. The difference is converted into a small signal current, which goes through a first-stage of current mirror to be amplified by K1, and through a second-stage of current mirror to be amplified by K2. The amplified signal is used to regulate the gate of the adjustment transistor MP. The error amplifier EA with the super transconductance structure is used to expand the bandwidth of the error amplifier EA.