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    Power Semiconductor Devices with Low Specific On-Resistance
    21.
    发明申请
    Power Semiconductor Devices with Low Specific On-Resistance 有权

    公开(公告)号：US20210273095A1

    公开(公告)日：2021-09-02

    申请号：US16877516

    申请日：2020-05-19

    Applicant: University of Electronic Science and Technology of China

    Inventor： Ming QIAO ,  Longfei LIANG ,  Yilei LYU ,  Zhao QI ,  Bo Zhang

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/04

    Abstract: A low specific on-resistance (Ron,sp) power semiconductor device includes a power device and a transient voltage suppressor (TVS); wherein the power device comprises a gate electrode, a drain electrode, a bulk electrode, a source electrode and a parasitic body diode, the bulk electrode and the source electrode are shorted, the TVS comprises an anode electrode and a cathode electrode, the drain electrode of the power device and the anode electrode of the TVS are connected by a first metal to form a high-voltage terminal electrode, the source electrode of the power device and the cathode electrode of the TVS are connected by a second metal to form a low-voltage terminal electrode.

    Power semiconductor devices
    23.
    发明授权
    Power semiconductor devices 有权

    公开(公告)号：US10608106B2

    公开(公告)日：2020-03-31

    申请号：US15955706

    申请日：2018-04-18

    Applicant: University of Electronic Science and Technology of China

    Inventor： Ming Qiao ,  Zhengkang Wang ,  Ruidi Wang ,  Zhao Qi ,  Bo Zhang

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

    Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.

    Multi-level gate driver applied to SiC MOSFET
    24.
    发明授权
    Multi-level gate driver applied to SiC MOSFET 有权

    公开(公告)号：US12199150B2

    公开(公告)日：2025-01-14

    申请号：US17848422

    申请日：2022-06-24

    Applicant: University of Electronic Science and Technology of China

    Inventor： Zekun Zhou ,  Jianwen Cao ,  Yue Shi ,  Bo Zhang

    IPC: H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

    Transient response enhancement circuit for buck-type voltage converters
    26.
    发明授权
    Transient response enhancement circuit for buck-type voltage converters 有权

    公开(公告)号：US10924002B2

    公开(公告)日：2021-02-16

    申请号：US16676470

    申请日：2019-11-07

    Applicant: University of Electronic Science and Technology of China

    Inventor： Zekun Zhou ,  Junyuan Rong ,  Zuao Wang ,  Yue Shi ,  Zhuo Wang ,  Bo Zhang

    IPC: H02M1/32 ,  H02M3/04 ,  H02M3/156

    Abstract: A transient response enhancement circuit for buck-type voltage converters, wherein, the transient load changing detecting module detects the output voltage of the buck-type voltage converter. The first control signal is generated when the increase of the output voltage is detected, and the second control signal is generated when the decrease of the output voltage is detected, thereby self-adaptively detecting the time of the buck-type voltage converter in response to the load changing. The compensation voltage predicting operation module predicts and adjusts the compensation voltage and the adjusted compensation voltage is superimposed on the buck-type voltage converter through the internal active compensation module to adjust the duty ratio of the buck-type voltage converter. The drive controlling insertion logic module can further improve the response speed.

    Segmented direct gate drive circuit of a depletion mode GaN power device
    27.
    发明授权
    Segmented direct gate drive circuit of a depletion mode GaN power device 有权

    公开(公告)号：US10911045B1

    公开(公告)日：2021-02-02

    申请号：US17005350

    申请日：2020-08-28

    Applicant: University of Electronic Science and Technology of China

    Inventor： Xin Ming ,  Bo Zhang ,  Qifei Xu ,  Shuai Mao ,  Xudong Feng ,  Zhuo Wang

    IPC: H03K17/687

    Abstract: A segmented direct gate drive circuit of a depletion mode GaN power device, a gate voltage of the GaN power device is charged from a negative voltage turn-off level to a threshold voltage of the GaN power device; when the gate voltage of the GaN power device is charged to the threshold voltage of the GaN power device, a current mirror charging module first turns on less than N of charging current mirror modules to charge the gate voltage of the GaN power device from the threshold voltage of the GaN power device to a Miller platform voltage of the GaN power device, and turns on N charging current mirror modules to charge the gate voltage of the GaN power device from the Miller platform voltage of the GaN power device to a zero level.

    Predictive dead time generating circuit
    28.
    发明授权
    Predictive dead time generating circuit 有权

    公开(公告)号：US10530258B1

    公开(公告)日：2020-01-07

    申请号：US16392664

    申请日：2019-04-24

    Applicant: University of Electronic Science and Technology of China

    Inventor： Zekun Zhou ,  Yunkun Wang ,  Yandong Yuan ,  Shilei Li ,  Zhuo Wang ,  Bo Zhang

    IPC: H02M1/38 ,  H02M3/158 ,  H02M1/00 ,  H02M3/156

    Abstract: A predictive dead time generating circuit includes a dead time detecting module configured to detect a dead time between the switching off of the upper power transistor and the switching on of the lower power transistor, and a dead time between the switching off of the lower power transistor and the switching on of the upper power transistor, and to generate a first detecting signal and a second detecting signal according to the condition of whether the detected dead time reaches an optimal value. The logic control module changes the output of the delay module according to the judgment result of the dead time detecting module, so as to change the dead time between the driving signal of the upper power transistor and the driving signal of the lower power transistor.

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