公开(公告)号：US20220246839A1

公开(公告)日：2022-08-04

申请号：US17725511

申请日：2022-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

公开(公告)号：US20220140002A1

公开(公告)日：2022-05-05

申请号：US17106214

申请日：2020-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20210151666A1

公开(公告)日：2021-05-20

申请号：US17141194

申请日：2021-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

公开(公告)号：US20190140074A1

公开(公告)日：2019-05-09

申请号：US15838243

申请日：2017-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Yao-Hsien Chung ,  Fu-Yu Tsai

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.

公开(公告)号：US10283618B1

公开(公告)日：2019-05-07

申请号：US15838243

申请日：2017-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Yao-Hsien Chung ,  Fu-Yu Tsai

IPC: H01L21/338 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.

公开(公告)号：US20170243952A1

公开(公告)日：2017-08-24

申请号：US15592150

申请日：2017-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Fu-Yu Tsai

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

公开(公告)号：US12205909B2

公开(公告)日：2025-01-21

申请号：US18138752

申请日：2023-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US20250008743A1

公开(公告)日：2025-01-02

申请号：US18885727

申请日：2024-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the first thickness is greater than the second thickness

公开(公告)号：US12108691B2

公开(公告)日：2024-10-01

申请号：US18324173

申请日：2023-05-26

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US12016250B2

公开(公告)日：2024-06-18

申请号：US17725511

申请日：2022-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.