公开(公告)号：US10008615B1

公开(公告)日：2018-06-26

申请号：US15437740

申请日：2017-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Sheng Feng ,  Chi-Cheng Huang ,  Ping-Chia Shih ,  Hung-Wei Lin ,  Yu-Chun Chen ,  Ling-Hsiu Chou ,  An-Hsiu Cheng

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.

公开(公告)号：US20170194511A1

公开(公告)日：2017-07-06

申请号：US15007280

申请日：2016-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Chun-Hung Cheng ,  Yu-Chieh Lin ,  Ya-Sheng Feng ,  Ping-Chia Shih ,  Ling-Hsiu Chou

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/6656 ,  H01L29/66833

Abstract: A non-volatile memory (NVM) device includes a substrate, a charge trapping structure, a first gate electrode and a spacer. The charge trapping structure is disposed on the substrate. The first gate electrode is disposed on the charge trapping structure. The spacer is disposed on at least one sidewall of the first gate electrode and the charge trapping structure. Wherein, the charge trapping structure has a lateral size substantially greater than that of the first gate electrode.

公开(公告)号：US09412851B2

公开(公告)日：2016-08-09

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。

公开(公告)号：US20150024598A1

公开(公告)日：2015-01-22

申请号：US13943900

申请日：2013-07-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Fang Chung ,  Ping-Chia Shih ,  Hsiang-Chen Lee ,  Che-Hao Chang ,  Jhih-Long Lin ,  Wei-Pin Huang ,  Shao-Nung Huang ,  Yu-Cheng Wang ,  Jaw-Jiun Tu ,  Chung-Che Huang

IPC: H01L21/306

CPC classification number: H01L21/306 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/66825

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Abstract translation: 提供一种制造半导体器件的方法。 提供了具有第一区域和第二多晶硅层的基板，第一区域具有第一多晶硅层和第二区域。 然后在第二区域中的第一区域中的第一多晶硅层的第一多晶硅层之上沉积氮化物HM膜，并在第二区域中的第二多晶硅层上方沉积氮化物HM膜。 之后，在第一区域中的氮化物HM膜上形成第一图案化钝化物以覆盖氮化物HM膜和第一器件，并且在第二区域中的第二多晶硅层之上形成第二图案化钝化。 第二区域中的第二多晶硅层由第二图案化钝化限定。

公开(公告)号：US20240006345A1

公开(公告)日：2024-01-04

申请号：US17874299

申请日：2022-07-27

Applicant: United Microelectronics Corp.

Inventor： Po Hsien Chen ,  Ping-Chia Shih ,  Che Hao Kuo ,  Chia-Min Hung ,  Ching-Hua Yeh ,  Wan-Chun Liao

IPC: H01L23/00 ,  H04L9/32 ,  H01L29/06

CPC classification number: H01L23/57 ,  H04L9/3278 ,  H01L29/0649

Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

公开(公告)号：US11616069B2

公开(公告)日：2023-03-28

申请号：US17073443

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Kuei-Ya Chuang ,  Chuang-Hsin Chueh ,  Ming-Che Tsai ,  Wen-Lin Wang ,  Yi-Chun Teng ,  Ssu-Yin Liu ,  Wan-Chun Liao

IPC: H01L27/11521

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

公开(公告)号：US20220293615A1

公开(公告)日：2022-09-15

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US10177165B1

公开(公告)日：2019-01-08

申请号：US15641560

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Ming-Hua Tsai ,  Wan-Chun Liao

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/266 ,  H01L21/28 ,  H01L29/51

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

公开(公告)号：US20180053771A1

公开(公告)日：2018-02-22

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US20150179748A1

公开(公告)日：2015-06-25

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。