公开(公告)号：US09875909B1

公开(公告)日：2018-01-23

申请号：US15220365

申请日：2016-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/321 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/302 ,  H01L21/306

CPC classification number: H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US09466484B1

公开(公告)日：2016-10-11

申请号：US14859491

申请日：2015-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Yu-Ting Li ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Wu-Sian Sie ,  I-Lun Hung ,  Chun-Tsen Lu ,  Shih-Ming Lin ,  Lan-Ping Chang

IPC: H01L21/31 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/1116

Abstract: A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A plurality of fin structures are formed in a first area and a second area of a substrate. A first density of the fin structures in the first area is lower than a second density of the fin structures in the second area. A gate dielectric layer is formed on the fin structures. An amorphous silicon layer is formed on the gate dielectric layer and the fin structures in the first area and the second area. Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser. The crystalline silicon layer disposed in the first area and the amorphous silicon layer disposed in the second area are polished.

Abstract translation: 提供一种半导体器件的制造方法。 该制造方法包括以下步骤。 在基板的第一区域和第二区域中形成多个翅片结构。 第一区域中的翅片结构的第一密度低于第二区域中的翅片结构的第二密度。 栅极电介质层形成在鳍结构上。 在第一区域和第二区域中的栅介质层和鳍结构上形成非晶硅层。 设置在第一区域中的非晶硅层的一部分被退火以通过激光形成晶体硅层。 设置在第一区域中的结晶硅层和设置在第二区域中的非晶硅层被抛光。

公开(公告)号：US09384996B2

公开(公告)日：2016-07-05

申请号：US14272672

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Kun-Ju Li ,  Chang-Hung Kung ,  Yue-Han Wu ,  Chih-Chien Liu

IPC: H01L21/3105 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/3105 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

Abstract translation: 提供一种制造半导体器件的方法及其制造方法。 根据实施例，提供具有至少具有多个第一栅极的第一区域和具有多个第二栅极的第二区域的衬底，其中相邻的第一栅极和相邻的第二栅极由绝缘体隔开，并且顶部 绝缘体的表面具有多个凹部。 然后，在第一栅极，第二栅极和绝缘体上形成覆盖层，并填充凹部。 去除覆盖层直到达到绝缘体的顶表面，从而形成填充凹部的绝缘沉积物，其中绝缘沉积物的上表面基本上与绝缘体的顶表面对准。

公开(公告)号：US20160027679A1

公开(公告)日：2016-01-28

申请号：US14444131

申请日：2014-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Kun-Ju Li ,  Wu-Sian Sie ,  Yi-Liang Liu

IPC: H01L21/683 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02227 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76251 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381

Abstract: A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer.

Abstract translation: 提供了修复氧化物层的方法和制造施加氧化物层的半导体结构体的方法。 修复氧化物层的方法包括以下步骤。 首先，提供具有第一区域和第二区域的载体，其中在第二区域上形成修复氧化物层。 然后，载体附着到其上形成有待修复的氧化物层的基板上，其中载体和基板通过修复氧化物层和待修复的氧化物层彼此附接。 此后，将要修复的氧化物层与修复氧化物层结合。

公开(公告)号：US20150325574A1

公开(公告)日：2015-11-12

申请号：US14272672

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Kun-Ju Li ,  Chang-Hung Kung ,  Yue-Han Wu ,  Chih-Chien Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/3105 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.

Abstract translation: 提供了一种制造半导体器件的方法及其制造方法。 根据实施例，提供具有至少具有多个第一栅极的第一区域和具有多个第二栅极的第二区域的衬底，其中相邻的第一栅极和相邻的第二栅极由绝缘体隔开，并且顶部 绝缘体的表面具有多个凹部。 然后，在第一栅极，第二栅极和绝缘体上形成覆盖层，并填充凹部。 去除覆盖层，直到到达绝缘体的顶表面，从而形成填充凹部的绝缘沉积物，其中绝缘沉积物的上表面基本上与绝缘体的顶表面对准。

公开(公告)号：US20150079780A1

公开(公告)日：2015-03-19

申请号：US14026634

申请日：2013-09-13

Applicant: United Microelectronics Corp.

Inventor： Yl-Liang Liu ,  Wu-Sian Sie ,  Po-Cheng Huang ,  Chih-Hsien Chen ,  I-Lun Hung ,  Yen-Ming Chen ,  Yu-Ting Li ,  Chang-Hung Kung ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/78

Abstract: A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed.

Abstract translation: 公开了一种形成半导体器件的方法。 在基板上形成栅极结构。 栅极结构包括在虚拟栅极的侧壁处的伪栅极和间隔物。 在栅极结构外部的基板上形成电介质层。 形成金属硬掩模层以覆盖电介质层和间隔物的顶部并露出栅极结构的表面。 去除伪栅极以形成栅极沟槽。 在填充在栅极沟槽中的金属硬掩模层上形成低电阻率金属层。 除去栅极沟槽外的低电阻率金属层。 去除金属硬掩模层。

公开(公告)号：US08940600B2

公开(公告)日：2015-01-27

申请号：US14294152

申请日：2014-06-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

IPC: H01L27/06

CPC classification number: H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在衬底的电阻器区域上形成浅沟槽隔离（STI）; 在STI中形成坦克; 并且在罐内形成电阻器，并在罐外部的STI的顶表面的两侧形成电阻器。

公开(公告)号：US10943910B2

公开(公告)日：2021-03-09

申请号：US16151337

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US10734276B2

公开(公告)日：2020-08-04

申请号：US15862564

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Fu-Shou Tsai ,  Wen-Chin Lin ,  Chun-Liang Liu

IPC: H01L21/768 ,  H01L27/108 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/762

Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

公开(公告)号：US09972498B2

公开(公告)日：2018-05-15

申请号：US15081932

申请日：2016-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Po-Cheng Huang ,  Kun-Ju Li ,  Wen-Chin Lin

IPC: B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/28247 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31053 ,  H01L21/31056 ,  H01L29/66545

Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.