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    Uncore microcode ROM
    21.
    发明授权
    Uncore microcode ROM 有权
    Uncore微码ROM

    公开(公告)号：US09483263B2

    公开(公告)日：2016-11-01

    申请号：US14072428

    申请日：2013-11-05

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  John D. Bunda ,  Brent Bean

    IPC: G06F9/00 ,  G06F9/44 ,  G06F9/26 ,  G06F9/30

    CPC classification number: G06F9/26 ,  G06F9/30145 ,  G06F9/30174

    Abstract: A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.

    Abstract translation: 微处理器包括多个处理核心，每个处理核心包括物理上位于核心内并由核心读取但不能被其他核心（“核心存储器”）读取的对应存储器。 微处理器还包括物理上位于所有核心外的所有核心（“非存储器”）可读取的存储器。 对于每个核心，非核存储器和对应的核心存储器共同提供M个字节的存储器，用于由核心获取的微代码指令，如下：非存储器提供微代码指令存储器的M个字节的J，并且相应的核心存储器提供K M码的微码指令存储。 J，K和M是计数数，M = J + K。 存储器是非架构可见的，并且使用由非架构程序计数器提供的提取地址来访问，并且微代码指令是实施架构指令的非架构指令。

    Multi-core synchronization mechanism
    22.
    发明授权
    Multi-core synchronization mechanism 有权
    多核同步机制

    公开(公告)号：US09465432B2

    公开(公告)日：2016-10-11

    申请号：US14281434

    申请日：2014-05-19

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F1/04 ,  G06F1/32 ,  G06F9/52 ,  G06F12/08

    CPC classification number: G06F1/3287 ,  G06F1/04 ,  G06F1/32 ,  G06F9/522 ,  G06F12/0891 ,  G06F2212/1028 ,  G06F2212/60

    Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

    Abstract translation: 微处理器包括控制单元，该控制单元被配置为选择性地将各个时钟信号控制到多个处理核心中的每一个。 每个处理核心被配置为分别向控制单元写入一个值。 对于所述多个处理核心的每个核心，所述控制单元被配置为响应于所述核心向所述控制单元写入值而将相应的时钟信号关断到所述核心。 控制单元被配置为检测当所有处理核心已经向控制单元写入值并且控制单元已经将各个时钟信号截止到所有处理核心时发生的状况。 控制单元被配置为响应于检测到所发生的状况，同时将各个时钟信号接通到所有处理核心。

    Processor that performs approximate computing instructions
    23.
    发明授权
    Processor that performs approximate computing instructions 有权
    执行近似计算指令的处理器

    公开(公告)号：US09389863B2

    公开(公告)日：2016-07-12

    申请号：US14522512

    申请日：2014-10-23

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

    IPC: G06F9/30 ,  G06F11/07

    CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30185 ,  G06F9/30189 ,  G06F11/0721 ,  G06F11/0793

    Abstract: A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.

    Abstract translation: 一种处理器包括一个译码器，该解码器解码指示处理器以近似方式执行后续计算的指令，以及响应该指令以近似方式执行后续计算的功能单元。 指令指示处理器清除与存储在处理器的通用寄存器中的值相关联的错误量。 错误量表示与处理器以近似的方式执行的计算结果相关联的错误量。 处理器还会根据指令清除错误量。 另一个指令指定要执行的计算，并且包括指示处理器以近似的方式执行计算的前缀。 功能单元以由前缀指定的近似方式执行由指令指定的计算。

    MICROPROCESSOR THAT FUSES IF-THEN INSTRUCTIONS
    25.
    发明申请
    MICROPROCESSOR THAT FUSES IF-THEN INSTRUCTIONS 有权
    如果说明说明书的话，MICROPROCESSOR FUSES

    公开(公告)号：US20140351561A1

    公开(公告)日：2014-11-27

    申请号：US14066520

    申请日：2013-10-29

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Terry Parks ,  G. Glenn Henry

    IPC: G06F9/30

    CPC classification number: G06F9/30145 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3836

    Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.

    Abstract translation: 微处理器包括指令翻译单元，其从IT指令中提取条件信息，并使IT指令与第一IT块指令融合。 对于IT块的每个指令，指令转换单元使用从IT指令提取的条件信息来确定IT块指令的相应条件，并将IT块指令转换成微指令。 微指令包括各自的条件。 执行单元根据各自的条件有条件地执行微指令。 对于每个IT块指令，指令转换单元使用提取的条件信息来确定各自的状态值。 状态值包括具有左移N-1位的低5位的IT指令的低8位，其中N表示IT块指令在IT块中的位置。

    UNCORE MICROCODE ROM
    28.
    发明申请
    UNCORE MICROCODE ROM 有权

    公开(公告)号：US20140297993A1

    公开(公告)日：2014-10-02

    申请号：US14072428

    申请日：2013-11-05

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  John D. Bunda ,  Brent Bean

    IPC: G06F9/30

    CPC classification number: G06F9/26 ,  G06F9/30145 ,  G06F9/30174

    Abstract: A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.

    Abstract translation: 微处理器包括多个处理核心，每个处理核心包括物理上位于核心内并由核心读取但不能被其他核心（“核心存储器”）读取的对应存储器。 微处理器还包括物理上位于所有核心外的所有核心（“非存储器”）可读取的存储器。 对于每个核心，非核存储器和对应的核心存储器共同提供M个字节的存储器，用于由核心获取的微代码指令，如下：非存储器提供微代码指令存储器的M个字节的J，并且相应的核心存储器提供K M码的微码指令存储。 J，K和M是计数数，M = J + K。 存储器是非架构可见的，并且使用由非架构程序计数器提供的提取地址来访问，并且微代码指令是实施架构指令的非架构指令。

    Microprocessor that fuses if-then instructions
    29.
    发明授权
    Microprocessor that fuses if-then instructions 有权

    公开(公告)号：US10394562B2

    公开(公告)日：2019-08-27

    申请号：US15728551

    申请日：2017-10-10

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A microprocessor performs an If-Then (IT) instruction and an associated IT block by extracting condition information from the IT instruction and for each instruction of the IT block: determining a respective condition for the instruction using the extract condition information, translating the instruction into a microinstruction, and conditionally executing the microinstruction based on the respective condition. For a first instruction, the translating comprises fusing the IT instruction with the first IT block instruction. A hardware instruction translation unit performs the extracting, determining and translating. Execution units conditionally execute the microinstructions. The hardware instruction translation unit and execution units are distinct hardware elements and are coupled together. The hardware translation unit performs the extracting, fusing and for each instruction of the IT block the determining and translating without writing intermediate results to a system memory, without execution of other architectural instructions by the microprocessor, and/or in six clock cycles or less.

    Dynamic Reconfiguration of Multi-core Processor
    30.
    发明申请
    Dynamic Reconfiguration of Multi-core Processor 审中-公开

    公开(公告)号：US20190095216A1

    公开(公告)日：2019-03-28

    申请号：US16203819

    申请日：2018-11-29

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Darius D. Gaskins

    IPC: G06F9/38 ,  G06F9/4401 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/30 ,  G06F12/0808 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F12/0875 ,  G06F13/364 ,  G06F21/57 ,  H04L9/08 ,  G06F21/53 ,  H01L21/66

    Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

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