公开(公告)号：US20050079677A1

公开(公告)日：2005-04-14

申请号：US10683901

申请日：2003-10-10

申请人： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

发明人： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

摘要： A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

公开(公告)号：US20050035470A1

公开(公告)日：2005-02-17

申请号：US10639170

申请日：2003-08-12

申请人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

发明人： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/8238 ,  H01L27/088

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

摘要： A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

摘要翻译： 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

公开(公告)号：US20060286740A1

公开(公告)日：2006-12-21

申请号：US11467980

申请日：2006-08-29

申请人： Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

发明人： Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

摘要翻译： 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US20050045965A1

公开(公告)日：2005-03-03

申请号：US10831021

申请日：2004-04-23

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

摘要翻译： 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US20050035345A1

公开(公告)日：2005-02-17

申请号：US10832020

申请日：2004-04-26

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/06

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

摘要翻译： 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

公开(公告)号：US07459756B2

公开(公告)日：2008-12-02

申请号：US11467980

申请日：2006-08-29

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC分类号： H01L29/76

CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

摘要翻译： 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US07335929B2

公开(公告)日：2008-02-26

申请号：US10967917

申请日：2004-10-18

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01L31/00

CPC分类号： H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

摘要： A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

摘要翻译： 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

公开(公告)号：US20060177997A1

公开(公告)日：2006-08-10

申请号：US11377105

申请日：2006-03-16

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC分类号： H01L21/20

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

摘要翻译： 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

公开(公告)号：US20050035369A1

公开(公告)日：2005-02-17

申请号：US10729092

申请日：2003-12-05

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L31/0328

CPC分类号： H01L29/6653 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1104 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

摘要： A semiconductor device or circuit is formed on a semiconductor substrate with first and second semiconductor materials having different lattice-constants. A first transistor includes a channel region formed oppositely adjacent a source and drain region. At least a portion of the source and drain regions are formed in the second semiconductor material thereby forming lattice-mismatched zones in the first transistor. A second component is coupled to the transistor to form a circuit, e.g., an inverter. The second component can be a second transistor having a conductivity type differing from the first transistor or a resistor.

摘要翻译： 半导体器件或电路在具有不同晶格常数的第一和第二半导体材料的半导体衬底上形成。 第一晶体管包括与源区和漏区相对地形成的沟道区。 源区和漏区的至少一部分形成在第二半导体材料中，从而在第一晶体管中形成晶格失配区。 第二分量耦合到晶体管以形成电路，例如逆变器。 第二部件可以是具有不同于第一晶体管或电阻器的导电类型的第二晶体管。

公开(公告)号：US08062946B2

公开(公告)日：2011-11-22

申请号：US11093847

申请日：2005-03-30

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC分类号： H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

摘要： A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

摘要翻译： 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，其包含具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。