公开(公告)号：US07314813B2

公开(公告)日：2008-01-01

申请号：US10976539

申请日：2004-10-29

Applicant: Chin-Ta Su ,  Jerry Lai ,  Yu-Lin Yen

Inventor： Chin-Ta Su ,  Jerry Lai ,  Yu-Lin Yen

IPC: H01L21/20

CPC classification number: H01L21/76816 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/7685

Abstract: A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.

Abstract translation: 提供了一种形成半导体器件的方法，该半导体器件通过在金属层上并入多层抗反射涂层来减少金属应力诱导的光失准。 该方法包括：在衬底上形成导电层的衬底，沉积多层抗反射涂层（包括钛和氮化钛的交替层），与第一蚀刻步骤相结合形成多条导电线，沉积 介电层，并且与第二蚀刻步骤相关地限定至少一个通孔。

公开(公告)号：US20070054197A1

公开(公告)日：2007-03-08

申请号：US11223480

申请日：2005-09-08

Applicant: Yu-Lin Yen

Inventor： Yu-Lin Yen

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/36 ,  G03F1/32

Abstract: The present invention provides a mask comprising a substrate, a plurality of strip patterns and at least an assist pattern. The strip patterns are disposed on the substrate and arranged in parallel to one another. The assist pattern is in a strip shape and disposed on the substrate. The assist pattern is arranged in parallel to and outside of the outermost strip pattern of the strip patterns. The assist pattern and the strip pattern have the same phase, while the assist pattern has a width larger than that of the strip patterns. When the mask is applied for exposure process, the pattern of the assist pattern will not be transferred to the underlying layer to be exposed.

Abstract translation: 本发明提供了一种掩模，其包括基底，多个条状图案和至少一个辅助图案。 带状图案设置在基板上并且彼此平行地布置。 辅助图案为带状，并设置在基板上。 辅助图案平行于带状图案的最外面带状图案并排布置。 辅助图案和带状图案具有相同的相位，而辅助图案的宽度大于带状图案的宽度。 当掩模用于曝光处理时，辅助图案的图案将不会转移到要暴露的下层。

公开(公告)号：US09024437B2

公开(公告)日：2015-05-05

申请号：US13524985

申请日：2012-06-15

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/3128 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有多个侧面和多个拐角区域的基板，其中每个所述拐角区域位于所述基板的至少两个侧面的相交处; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及载体基板，其中所述基板设置在所述载体基板上，并且所述基板具有在至少一个所述拐角区域中朝向所述载体基板延伸的凹部。

公开(公告)号：US08698316B2

公开(公告)日：2014-04-15

申请号：US13190408

申请日：2011-07-25

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电焊盘; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08581386B2

公开(公告)日：2013-11-12

申请号：US13350690

申请日：2012-01-13

Applicant: Yu-Lin Yen ,  Shih-Ming Chen ,  Hsi-Chien Lin ,  Yu-Lung Huang ,  Tsang-Yu Liu

Inventor： Yu-Lin Yen ,  Shih-Ming Chen ,  Hsi-Chien Lin ,  Yu-Lung Huang ,  Tsang-Yu Liu

IPC: H01L23/04 ,  H01L23/12

CPC classification number: H01L31/0203 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L27/14685 ,  H01L31/048 ,  H01L2224/16 ,  H01L2924/1461 ,  Y02E10/50 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.

Abstract translation: 本发明的一个实施例提供了一种芯片封装，其包括：半导体衬底，具有与器件区域相邻的器件区域和非器件区域; 封装层，设置在所述半导体衬底上; 间隔层，设置在所述半导体衬底和所述封装层之间并且围绕所述器件区域和所述非器件区域; 设置在所述半导体衬底和所述封装层之间以及所述间隔层和所述器件区域之间并围绕所述非器件区域的一部分的环形结构; 以及包括形成在间隔层或环结构中的中空图案的辅助图案，位于间隔层和器件区域之间的材料图案，或其组合。

公开(公告)号：US08525345B2

公开(公告)日：2013-09-03

申请号：US13044457

申请日：2011-03-09

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括具有上表面和下表面的衬底，位于衬底中或其下表面下方的多个导电焊盘，位于导电焊盘之间的介电层，从上表面向下延伸的孔 表面并暴露一部分导电焊盘，以及导电层，其位于孔中并与导电焊盘电接触。

公开(公告)号：US08415088B2

公开(公告)日：2013-04-09

申请号：US11377159

申请日：2006-03-15

Applicant: Yu-Lin Yen

Inventor： Yu-Lin Yen

IPC: G06F7/26

CPC classification number: G03F7/091 ,  G03F7/095 ,  G03F7/168

Abstract: A method for forming a material layer with an anti-reflective layer as the top surface. The method comprises steps of providing a material layer and performing an ion implantation process to change a plurality of physical properties of a portion of the material layer near a top surface of the material layer so as to covert the portion of the material layer into an anti-reflective layer.

Abstract translation: 一种形成具有抗反射层作为顶表面的材料层的方法。 该方法包括以下步骤：提供材料层并执行离子注入工艺以改变材料层的顶表面附近的材料层的一部分的多个物理性能，以将材料层的该部分隐蔽成反层 反射层。

公开(公告)号：US20110156074A1

公开(公告)日：2011-06-30

申请号：US12981600

申请日：2010-12-30

Applicant: Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

Inventor： Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC: H01L33/60 ,  H01L33/48

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

Abstract translation: 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

公开(公告)号：US20080230860A1

公开(公告)日：2008-09-25

申请号：US11878568

申请日：2007-07-25

Applicant: Yu-Lin Yen ,  Chen-Mei Fan

Inventor： Yu-Lin Yen ,  Chen-Mei Fan

IPC: H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14618 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/14

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device, a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract translation: 本发明提供一种集成电路封装及其制造方法。 集成电路封装包括其上具有光敏器件的集成电路芯片; 形成在所述集成电路芯片的上表面上并且电连接到所述感光装置的焊盘，形成在所述焊盘和所述感光装置之间的屏障; 以及形成在集成电路芯片的侧壁上并电连接到接合焊盘的导电层。 阻挡层阻止粘合剂层溢出到形成有感光装置的区域中，以提高制造集成电路封装的成品率。