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13 条记录 (耗时 0.039 秒)

    Chip package and method for fabricating the same
    1.
    发明授权
    Chip package and method for fabricating the same 有权
    芯片封装及其制造方法

    公开(公告)号：US08575634B2

    公开(公告)日：2013-11-05

    申请号：US12981600

    申请日：2010-12-30

    申请人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

    发明人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

    IPC分类号： H01L33/60 ,  H01L33/48

    CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

    摘要翻译： 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

    CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME 有权
    芯片包装及其制造方法

    公开(公告)号：US20110156074A1

    公开(公告)日：2011-06-30

    申请号：US12981600

    申请日：2010-12-30

    申请人： Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

    发明人： Tsang-Yu LIU ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

    IPC分类号： H01L33/60 ,  H01L33/48

    CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

    摘要翻译： 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。

    Chip package and method for forming the same
    5.
    发明授权
    Chip package and method for forming the same 有权
    芯片封装及其形成方法

    公开(公告)号：US08890191B2

    公开(公告)日：2014-11-18

    申请号：US13536628

    申请日：2012-06-28

    申请人： Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang

    发明人： Chuan-Jin Shiu ,  Po-Shen Lin ,  Yi-Ming Chang

    IPC分类号： H01L33/00 ,  H01L21/00 ,  H01L27/146

    CPC分类号： H01L27/14618 ,  H01L27/1463 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.

    摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 形成在所述基板中的光电子器件; 设置在所述基板上的导电层，其中所述导电层电连接到所述光电子器件; 设置在所述基板和所述导电层之间的绝缘层; 遮光层，其设置在所述基板的所述第二表面上并与所述导电层直接接触，其中所述遮光层具有大于约80％的遮光率并且具有暴露所述导电层的至少一个开口; 以及布置在所述遮光层的开口中以与所述导电层电接触的导电凸块，其中所述遮光层和所述导电凸起部分都基本上完全覆盖所述基板的第二表面。

    Chip package and method for forming the same
    6.
    发明授权
    Chip package and method for forming the same 有权
    芯片封装及其形成方法

    公开(公告)号：US08900913B2

    公开(公告)日：2014-12-02

    申请号：US13588898

    申请日：2012-08-17

    申请人： Chuan-Jin Shiu ,  Po-Shen Lin ,  Shen-Yuan Mao ,  Cheng-Chi Peng

    发明人： Chuan-Jin Shiu ,  Po-Shen Lin ,  Shen-Yuan Mao ,  Cheng-Chi Peng

    IPC分类号： H01L33/00 ,  H01L21/00 ,  H01L27/146

    CPC分类号： H01L27/14618 ,  H01L2224/13 ,  H01L2933/0025

    摘要： An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least one optoelectronic device is formed in the substrate; forming an insulating layer on the substrate; forming a conducting layer on the insulating layer on the substrate, wherein the conducting layer is electrically connected to the at least one optoelectronic device; and spraying a solution of light shielding material on the second surface of the substrate to form a light shielding layer on the second surface of the substrate.

    摘要翻译： 本发明的一个实施例提供了一种用于形成芯片封装的方法，其包括：提供具有第一表面和第二表面的衬底，其中在衬底中形成至少一个光电器件; 在所述基板上形成绝缘层; 在所述基板上的所述绝缘层上形成导电层，其中所述导电层电连接到所述至少一个光电器件; 以及在所述基板的第二表面上喷射遮光材料的溶液，以在所述基板的第二表面上形成遮光层。

    Package structure for a chip and method for fabricating the same
    8.
    发明授权
    Package structure for a chip and method for fabricating the same 有权
    一种芯片的封装结构及其制造方法

    公开(公告)号：US08633558B2

    公开(公告)日：2014-01-21

    申请号：US12981640

    申请日：2010-12-30

    申请人： Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

    发明人： Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

    IPC分类号： H01L31/0216 ,  H01L31/18

    CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.

    摘要翻译： 该实施例提供了用于芯片的封装结构及其制造方法。 用于芯片的封装结构包括具有衬底和焊盘结构的芯片。 该芯片具有上表面和下表面。 上包装层覆盖芯片的上表面。 间隔层位于上包装层和芯片之间。 导电路径电连接到接合焊盘结构。 防反射层设置在间隔层和上包装层之间。 重叠区域在抗反射层和间隔层之间。

    Chip package
    9.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US08384174B2

    公开(公告)日：2013-02-26

    申请号：US13070375

    申请日：2011-03-23

    申请人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    发明人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    IPC分类号： H01L31/0203

    CPC分类号： H01L31/02164 ,  H01L27/14618 ,  H01L33/486 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/13

    摘要： A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.

    摘要翻译： 芯片封装包括：具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层，其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部，其中底部设置在开口中并与导电层电接触，并且上部位于开口的外侧，并沿远离 开口 从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层，在所述上部下方延伸，并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。

    CHIP PACKAGE
    10.
    发明申请
    CHIP PACKAGE 有权
    芯片包装

    公开(公告)号：US20110233770A1

    公开(公告)日：2011-09-29

    申请号：US13070375

    申请日：2011-03-23

    申请人： Hsin-Chih CHIU ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    发明人： Hsin-Chih CHIU ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    IPC分类号： H01L23/498

    CPC分类号： H01L31/02164 ,  H01L27/14618 ,  H01L33/486 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/13

    摘要： A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.

    摘要翻译： 芯片封装包括：具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层，其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部，其中底部设置在开口中并与导电层电接触，并且上部位于开口的外侧，并沿远离 开口 从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层，在所述上部下方延伸，并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。