APPARATUS WITH RESPONSE COMPLETION PACING
    21.
    发明公开

    公开(公告)号:US20240354006A1

    公开(公告)日:2024-10-24

    申请号:US18759793

    申请日:2024-06-28

    发明人: Ying Huang Mark Ish

    IPC分类号: G06F3/06

    摘要: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.

    Semiconductor die assemblies with decomposable materials and associated methods and systems

    公开(公告)号:US12125796B2

    公开(公告)日:2024-10-22

    申请号:US18507908

    申请日:2023-11-13

    摘要: Semiconductor die assemblies with decomposable materials, and associated methods and systems are disclosed. In an embodiment, a semiconductor die assembly includes a memory controller die carrying one or more memory dies attached to its first side. The semiconductor die assembly also includes a biodegradable structure attached to its second side opposite to the first side. The biodegradable structure includes a conductive material and an insulating material, both of which are biodegradable and disintegrate in a wet process. The biodegradable structure can be configured to couple the memory controller die with an interface die. In this manner, when the biodegradable structure disintegrates (e.g., dissolve) in the wet process, the memory controller carrying the memory dies can be separated from the interface die to reclaim the memory controller with the memory dies and the interface die.

    Semiconductor device having sense amplifier equipped with compensation circuit

    公开(公告)号:US12125521B2

    公开(公告)日:2024-10-22

    申请号:US17821775

    申请日:2022-08-23

    发明人: Kyoichi Nagata

    IPC分类号: G11C11/4091

    CPC分类号: G11C11/4091

    摘要: An apparatus that includes a sense amplifier including first and second cross-coupled transistors to amplify a potential difference between first and second digit lines, a compensation circuit configured to compensate a threshold difference between the first and second transistors, first and second local I/O lines coupled to the first and second digit lines, respectively, and an equalizing circuit configured to equalize the first and second local I/O lines. The equalizing circuit is configured to change a precharge level of the first and second local I/O lines from a first potential to a second potential before a compensation operation of the compensation circuit is completed.

    Multi-rail power transition
    26.
    发明授权

    公开(公告)号:US12125517B2

    公开(公告)日:2024-10-22

    申请号:US17804414

    申请日:2022-05-27

    摘要: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

    Techniques for accessing managed NAND

    公开(公告)号:US12124367B2

    公开(公告)日:2024-10-22

    申请号:US17262476

    申请日:2020-12-07

    IPC分类号: G06F12/00 G06F12/02 G06F12/06

    摘要: Methods, systems, and devices for techniques for accessing managed not-AND (NAND) memory are described. An indicator of a first type that indicates whether each physical address in a group of physical addresses stores valid data may be accessed. Indicators of a second type may be used to indicate whether respective physical addresses of the group of physical addresses store valid data. Data stored at the group of physical addresses may be transferred to a different group of physical addresses based on the indicator of the first type. Also, another indicator of the first type that indicates whether each physical address in the different group of physical addresses stores valid data may be updated.

    Transmission failure feedback schemes for reducing crosstalk

    公开(公告)号:US12124329B2

    公开(公告)日:2024-10-22

    申请号:US18211472

    申请日:2023-06-19

    IPC分类号: G06F11/10 G11C29/42

    摘要: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

    PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICE

    公开(公告)号:US20240347116A1

    公开(公告)日:2024-10-17

    申请号:US18755046

    申请日:2024-06-26

    IPC分类号: G11C16/34 G11C16/04

    CPC分类号: G11C16/3431 G11C16/0483

    摘要: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising identifying one or more valid pages of a first block, the first block being associated with a first management unit of the memory device; responsive to determining that a data integrity metric value associated with the first block satisfies a threshold criterion, causing the memory device to copy data from the one or more valid pages to a destination set of pages associated with a second block of a second management unit; marking each page of the one or more valid pages as invalid; and performing an error correcting operation, using one or more invalid pages of the first block, on a third block of the first management unit.

    PERFORMING DATA INTEGRITY CHECKS TO IDENTIFY DEFECTIVE WORDLINES

    公开(公告)号:US20240347110A1

    公开(公告)日:2024-10-17

    申请号:US18755062

    申请日:2024-06-26

    摘要: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits programmed in the first logical level fails to satisfy a threshold criterion, performing a write operation on the second wordline to program second data.