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公开(公告)号:US20240354006A1
公开(公告)日:2024-10-24
申请号:US18759793
申请日:2024-06-28
发明人: Ying Huang , Mark Ish
IPC分类号: G06F3/06
CPC分类号: G06F3/0613 , G06F3/0611 , G06F3/0659 , G06F3/0679
摘要: Methods, apparatuses and systems related to response completion pacing for latency control are described. The apparatus may utilize response completion pacing to dynamically control timing of output communications to the host. In some embodiments, the memory device can include a ready response queue that temporarily stores the data retrieved from a backend portion or a storage portion of the memory device. The apparatus can include logic coupled to the ready response queue and configured to communicate/send the data in the ready response queue according to a cadence period. In some embodiments, the logic can further dynamically adjust a storage capacity of the ready response queue and/or the cadence period.
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公开(公告)号:US20240353914A1
公开(公告)日:2024-10-24
申请号:US18762482
申请日:2024-07-02
IPC分类号: G06F1/3287 , G06F1/28 , G06F1/3234 , G11C11/22 , G11C11/4096
CPC分类号: G06F1/3287 , G06F1/28 , G06F1/3275 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/4096
摘要: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.
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23.
公开(公告)号:US12125796B2
公开(公告)日:2024-10-22
申请号:US18507908
申请日:2023-11-13
发明人: Fatma Arzum Simsek-Ege , Luoqi Li , Marsela Pontoh
IPC分类号: H01L23/31 , H01L23/538 , H01L25/065
CPC分类号: H01L23/5385 , H01L23/31 , H01L23/5384 , H01L23/5386 , H01L25/0657
摘要: Semiconductor die assemblies with decomposable materials, and associated methods and systems are disclosed. In an embodiment, a semiconductor die assembly includes a memory controller die carrying one or more memory dies attached to its first side. The semiconductor die assembly also includes a biodegradable structure attached to its second side opposite to the first side. The biodegradable structure includes a conductive material and an insulating material, both of which are biodegradable and disintegrate in a wet process. The biodegradable structure can be configured to couple the memory controller die with an interface die. In this manner, when the biodegradable structure disintegrates (e.g., dissolve) in the wet process, the memory controller carrying the memory dies can be separated from the interface die to reclaim the memory controller with the memory dies and the interface die.
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24.
公开(公告)号:US12125539B2
公开(公告)日:2024-10-22
申请号:US17861467
申请日:2022-07-11
CPC分类号: G11C16/10 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483
摘要: A processing device determines a measured bit error count (BEC) value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system. The measured BEC value of the portion of the programming voltage distribution is compared to a threshold BEC value to generate a comparison result. In view of the comparison result, an adjusted program start voltage level is determined by adjusting a default program voltage level of a programming process. The programming process including a series of programming pulses is executed, where the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.
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公开(公告)号:US12125521B2
公开(公告)日:2024-10-22
申请号:US17821775
申请日:2022-08-23
发明人: Kyoichi Nagata
IPC分类号: G11C11/4091
CPC分类号: G11C11/4091
摘要: An apparatus that includes a sense amplifier including first and second cross-coupled transistors to amplify a potential difference between first and second digit lines, a compensation circuit configured to compensate a threshold difference between the first and second transistors, first and second local I/O lines coupled to the first and second digit lines, respectively, and an equalizing circuit configured to equalize the first and second local I/O lines. The equalizing circuit is configured to change a precharge level of the first and second local I/O lines from a first potential to a second potential before a compensation operation of the compensation circuit is completed.
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公开(公告)号:US12125517B2
公开(公告)日:2024-10-22
申请号:US17804414
申请日:2022-05-27
发明人: Kang-Yong Kim , Hyun Yoo Lee , Keun Soo Song
IPC分类号: G11C11/4074 , G11C11/4076 , G11C11/4093 , G11C11/4096
CPC分类号: G11C11/4074 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.
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公开(公告)号:US12124367B2
公开(公告)日:2024-10-22
申请号:US17262476
申请日:2020-12-07
发明人: Junjun Wang , Yi Heng Sun
CPC分类号: G06F12/0253 , G06F12/0238 , G06F12/0653
摘要: Methods, systems, and devices for techniques for accessing managed not-AND (NAND) memory are described. An indicator of a first type that indicates whether each physical address in a group of physical addresses stores valid data may be accessed. Indicators of a second type may be used to indicate whether respective physical addresses of the group of physical addresses store valid data. Data stored at the group of physical addresses may be transferred to a different group of physical addresses based on the indicator of the first type. Also, another indicator of the first type that indicates whether each physical address in the different group of physical addresses stores valid data may be updated.
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公开(公告)号:US12124329B2
公开(公告)日:2024-10-22
申请号:US18211472
申请日:2023-06-19
CPC分类号: G06F11/1044 , G06F11/1016 , G06F11/1028 , G11C29/42
摘要: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
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29.
公开(公告)号:US20240347116A1
公开(公告)日:2024-10-17
申请号:US18755046
申请日:2024-06-26
发明人: Wei Wang , Seungjune Jeon , Yang Liu , Charles See Yeung Kwong
CPC分类号: G11C16/3431 , G11C16/0483
摘要: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising identifying one or more valid pages of a first block, the first block being associated with a first management unit of the memory device; responsive to determining that a data integrity metric value associated with the first block satisfies a threshold criterion, causing the memory device to copy data from the one or more valid pages to a destination set of pages associated with a second block of a second management unit; marking each page of the one or more valid pages as invalid; and performing an error correcting operation, using one or more invalid pages of the first block, on a third block of the first management unit.
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公开(公告)号:US20240347110A1
公开(公告)日:2024-10-17
申请号:US18755062
申请日:2024-06-26
发明人: Jian Huang , Zhenming Zhou
CPC分类号: G11C16/102 , G11C16/08 , G11C16/26 , G11C29/4401 , G11C2029/1202
摘要: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits programmed in the first logical level fails to satisfy a threshold criterion, performing a write operation on the second wordline to program second data.
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