公开(公告)号：US20140146619A1

公开(公告)日：2014-05-29

申请号：US14168331

申请日：2014-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jui-Jen WU ,  Shau-Wei LU ,  Robert LO ,  Kun-Hsi LI

IPC分类号： G11C7/10

CPC分类号： G11C7/10 ,  G11C7/1015 ,  G11C11/412 ,  G11C11/413

摘要： A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.

摘要翻译： 写辅助单元包括配置成在写操作期间将数据从第一位线传送到第二位线的第一下拉电路。 写辅助单元进一步包括配置成在读操作期间将数据从第三位线传送到第四位线的第二下拉电路，其中写操作和读操作同时发生。 存储器件包括存储器阵列，存储器阵列包括第一位线和第二位线。 存储装置还包括连接到存储器阵列的写入辅助单元，其中写入辅助单元被配置为在读取操作中将写入操作中的第一位线的数据传送到第二位线，并且写入操作和 读操作同时发生。 存储器件还包括连接到写辅助单元的多路复用器。

公开(公告)号：US08570828B2

公开(公告)日：2013-10-29

申请号：US13008522

申请日：2011-01-18

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C8/00

CPC分类号： G11C7/1015 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2013/0088

摘要： A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.

摘要翻译： 存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。 每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。 可变数据宽度控制器与存储器通信。 可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。 要编程的每个位处于特定的逻辑状态。 当编程号码超过最大数量时，划分块将字分成两个或多个子字。 开关与分区块通信。 开关依次提供一个或多个写入脉冲。 每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

公开(公告)号：US08446755B2

公开(公告)日：2013-05-21

申请号：US13369253

申请日：2012-02-08

申请人： Richard S. Roy

发明人： Richard S. Roy

IPC分类号： G11C11/24 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1015 ,  G11C11/406 ,  G11C11/40618 ,  G11C2207/229

摘要： A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner.

摘要翻译： 一种通过执行不完整的写入操作来减少存储器单元的存储器周期时间的存储器系统。 在不完全写入操作期间，存储单元的存储节点上的电压未达到全电源电压。 随后通过一个或多个附加访问完成不完整的写入操作，其中存储节点上的电压被拉至完全电源电压。 可以通过以下方式完成不完整的写入操作：随后在空闲周期期间将相同的数据写入存储器单元; 随后将数据写入到与存储器单元相同的行中的其他存储单元; 随后从包括存储器单元的行读取数据; 或者在空闲周期期间刷新包含存储单元的行。 可能会迫使一个或多个空闲周期及时完成不完整的写入操作。

公开(公告)号：US20120320679A1

公开(公告)日：2012-12-20

申请号：US13474055

申请日：2012-05-17

申请人： Steven T. Sprouse ,  Sergey Anatolievich Gorobets ,  William Wu ,  Alan Bennett ,  Marielle Bundukin

发明人： Steven T. Sprouse ,  Sergey Anatolievich Gorobets ,  William Wu ,  Alan Bennett ,  Marielle Bundukin

IPC分类号： G11C16/04

CPC分类号： G11C7/1015 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7208 ,  G11C2216/14

摘要： A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.

摘要翻译： 公开了一种用于在保持期望的顺序读写性能水平的同时降低写入放大的系统和方法。 多银行闪存存储设备中的控制器可以接收用于写入多个闪存组的主机数据。 控制器可以将多个逻辑组中的接收数据组织成大于物理页面并且小于物理块，并且利用该条带化因子将主机数据的写入交织到存储体。 缓冲RAM与多存储体存储器的每个存储体相关联，其中缓冲器RAM的大小等于或大于多页逻辑组的大小。

公开(公告)号：US20110252206A1

公开(公告)日：2011-10-13

申请号：US13008522

申请日：2011-01-18

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G06F12/02 ,  G11C11/00

CPC分类号： G11C7/1015 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2013/0088

摘要： A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.

摘要翻译： 存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。 每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。 可变数据宽度控制器与存储器通信。 可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。 要编程的每个位处于特定的逻辑状态。 当编程号码超过最大数量时，划分块将字分成两个或多个子字。 开关与分区块通信。 开关依次提供一个或多个写入脉冲。 每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

公开(公告)号：US20110085367A1

公开(公告)日：2011-04-14

申请号：US12578940

申请日：2009-10-14

申请人： Timothy Richard Feldman ,  Wayne Howard Vinson

发明人： Timothy Richard Feldman ,  Wayne Howard Vinson

IPC分类号： G11C5/06 ,  G11C8/00

CPC分类号： G11C7/1012 ,  G06F13/1684 ,  G11C7/1015

摘要： A data storage system includes a plurality of memory devices for storing data. The plurality of memory devices is classified into a plurality of groups of memory devices. A control circuit is adapted to provide concurrent memory access operations to the plurality of memory devices. Each of a plurality of data channels is configured to provide a data path between the control circuit and one of the groups of memory devices. A plurality of switches is configured to connect and disconnect one of the memory devices in a select one of the groups of memory devices to one of the plurality of data channels and concurrently connect and disconnect another of the memory devices in the select group of memory devices to a different one of the plurality of data channels.

摘要翻译： 数据存储系统包括用于存储数据的多个存储器件。 多个存储器件被分为多组存储器件。 控制电路适于向多个存储器件提供并行存储器访问操作。 多个数据信道中的每一个被配置为在控制电路和存储器装置组之一之间提供数据路径。 多个开关被配置为将存储器设备组中的选择一个中的一个存储器件中的一个连接到多个数据通道中的一个，并同时连接和断开存储器设备组中的另一个存储器件 到多个数据信道中的不同的数据信道。

公开(公告)号：US07681006B2

公开(公告)日：2010-03-16

申请号：US08984563

申请日：1997-12-03

申请人： Jeffrey S. Mailloux ,  Kevin J. Ryan ,  Todd A. Merritt ,  Brett L. Williams

发明人： Jeffrey S. Mailloux ,  Kevin J. Ryan ,  Todd A. Merritt ,  Brett L. Williams

IPC分类号： G06F13/00

CPC分类号： G11C7/1027 ,  G11C7/1015 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/20

摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them.

摘要翻译： 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器并初始化设备以进行另一个突发访问。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。 此外，提供具有流水线和突发扩展数据输出操作模式的DRAM以及在它们之间切换的能力。

公开(公告)号：US20050219907A1

公开(公告)日：2005-10-06

申请号：US11135803

申请日：2005-05-24

申请人： Frankie Roohparvar

发明人： Frankie Roohparvar

IPC分类号： G11C7/10 ,  G11C11/34 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C7/1015 ,  G06F12/0246 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2216/22

摘要： A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

摘要翻译： 同步闪速存储器包括非易失性存储器单元阵列。 存储器阵列以行和列布置，并且可以进一步布置在可寻址块中。 数据通信连接用于与外部设备（例如处理器或其他存储器控制器）的双向数据通信。 写锁存器耦合在数据缓冲器和存储器阵列之间以锁存数据通信连接上提供的数据。 存储器可以将数据写入到诸如存储器阵列块的一个位置，同时从诸如第二存储器阵列块的第二位置读取数据。 写和读操作在数组块的公共可寻址行上执行。

公开(公告)号：US06839261B2

公开(公告)日：2005-01-04

申请号：US10648376

申请日：2003-08-27

申请人： Tsutomu Higuchi

发明人： Tsutomu Higuchi

IPC分类号： G01R31/28 ,  G06F12/00 ,  G06F12/06 ,  G11C7/10 ,  G11C16/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/56 ,  G11C5/02 ,  G11C5/06 ,  G11C8/00

CPC分类号： G11C16/26 ,  G11C7/1015 ,  G11C16/10 ,  G11C16/32 ,  G11C2029/5602

摘要： A semiconductor memory device comprises memory banks each including a memory cell array and a control circuit for the memory cell array and an interface circuit shared by the plural memory banks. The semiconductor memory device is adapted for performing reading of data from the plural memory banks and rewriting of data to the memory banks. In an operation mode for performing the reading, processings A1 to A4 are performed. In an operation mode for performing the rewriting, processings B1 to B3 are performed.

摘要翻译： 半导体存储器件包括各自包括存储单元阵列和用于存储单元阵列的控制电路和由多个存储体共享的接口电路的存储体。 半导体存储器件适于执行从多个存储体的数据读取和将数据重写到存储体。 在执行读取的操作模式中，执行处理A1至A4。 在执行重写的操作模式中，执行处理B1至B3。

公开(公告)号：US20040218418A1

公开(公告)日：2004-11-04

申请号：US10850011

申请日：2004-05-19

发明人： Timothy B. Cowles ,  Jeffrey P. Wright

IPC分类号： G11C011/00

CPC分类号： G11C11/406 ,  G11C7/1015 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/40611 ,  G11C11/40615 ,  G11C29/26 ,  G11C2029/2602

摘要： In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.