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    Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same
    22.
    发明申请
    Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same 有权
    具有集成高K金属栅极逻辑器件和无金属擦除栅极的非易失性分离栅极存储单元及其制造方法

    公开(公告)号：US20170025427A1

    公开(公告)日：2017-01-26

    申请号：US15180376

    申请日：2016-06-13

    申请人： Silicon Storage Technology, Inc.

    发明人： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/423

    CPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

    摘要翻译： 在具有HKMG逻辑门的逻辑和高电压器件的同一芯片上形成分离栅非易失性存储单元的方法。 该方法包括在芯片的存储器区域中形成用于擦除栅极和字线栅极的源极和漏极区域，浮动栅极，控制栅极和多晶硅层。 在存储区域上形成保护绝缘层，并且在芯片上形成HKMG层和多晶硅层，从存储区域移除，并在芯片的逻辑区域中图案化以形成具有不同量的底层绝缘体的逻辑门 。

    Method of making a non-volatile memory (NVM) with trap-up reduction
    23.
    发明授权
    Method of making a non-volatile memory (NVM) with trap-up reduction 有权
    制造具有陷阱减少的非易失性存储器（NVM）的方法

    公开(公告)号：US09548314B1

    公开(公告)日：2017-01-17

    申请号：US14945981

    申请日：2015-11-19

    申请人： FREESCALE SEMICONDUCTOR, INC.

    发明人： Cheong Min Hong ,  Konstantin V. Loiko ,  Juanyi Yin

    IPC分类号： H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L21/28

    CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/42328

    摘要： A method for forming a semiconductor device includes forming a select gate over a substrate and forming a charge storage layer and a control gate over the select gate. The charge storage layer and control gate overlap a first sidewall of the select gate and the charge storage layer is between the select gate and the control gate. A protective spacer is formed, wherein the protective spacer has a first portion adjacent a first sidewall of the charge storage layer and on the substrate, and the protective spacer is thinned. After thinning the protective spacer, a sidewall spacer is formed over the protective spacer, wherein the sidewall spacer has a first portion on the substrate, and the first portion of the protective spacer is between the first sidewall of the control gate and the first portion of the sidewall spacer.

    摘要翻译： 一种用于形成半导体器件的方法包括在衬底上形成选择栅极，并在选择栅极上形成电荷存储层和控制栅极。 电荷存储层和控制栅极与选择栅极的第一侧壁重叠，并且电荷存储层位于选择栅极和控制栅极之间。 形成保护间隔物，其中保护隔离物具有与电荷存储层的第一侧壁相邻的第一部分和基底上的保护间隔物，并且保护间隔物变薄。 在使保护间隔物变薄之后，在保护间隔物上方形成侧壁间隔物，其中侧壁间隔物在基底上具有第一部分，并且保护间隔物的第一部分位于控制栅极的第一侧壁和第一部分之间 侧壁间隔件。

    METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE
    24.
    发明申请
    METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE 有权
    用低功率逻辑器件形成分离式闪存存储器单元设备的方法

    公开(公告)号：US20160365350A1

    公开(公告)日：2016-12-15

    申请号：US15245539

    申请日：2016-08-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/423 ,  H01L21/3213

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

    摘要： A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.

    摘要翻译： 提供了一种制造嵌入式闪存设备的方法。 一对栅极叠层形成在半导体衬底上间隔开，并且在浮动栅极上包括浮动栅极和控制栅极。 在栅极堆叠和半导体衬底上形成公共栅极层，并且栅极堆叠的衬里侧壁。 在公共栅极层中执行第一蚀刻，以将公共栅极层的上表面分别凹入栅极堆叠的下表面，并在栅极堆叠之间形成擦除栅极。 硬掩模分别形成在擦除栅极，公共栅极层的字线区域和公共栅极层的逻辑门极区域上。 第二蚀刻被执行到具有硬掩模的公共栅层中，以同时形成字线和逻辑门。

    Method for forming a split-gate flash memory cell device with a low power logic device
    25.
    发明授权
    Method for forming a split-gate flash memory cell device with a low power logic device 有权
    用于形成具有低功率逻辑器件的分闸式闪存单元器件的方法

    公开(公告)号：US09484352B2

    公开(公告)日：2016-11-01

    申请号：US14573208

    申请日：2014-12-17

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Harry-Hak-Lay Chuang ,  Chang-Ming Wu ,  Shih-Chang Liu

    IPC分类号： H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11541 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

    摘要： An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

    摘要翻译： 提供了一种嵌入式闪存设备。 栅极堆叠包括布置在浮动栅极上的控制栅极。 擦除栅极邻近栅堆叠的第一侧布置。 字线布置成与栅堆叠的与第一侧相对的第二侧相邻。 字线包括字线凸出部，该字线突出部相对于字线的顶表面减小高度，并且与字线堆叠在字线的相反侧。 多晶硅逻辑门具有大致均匀的字线凸缘的顶表面。 ILD层布置在栅极堆叠，擦除栅极，多晶硅逻辑门和字线之上。 一个触点延伸穿过ILD层。 还提供了一种制造嵌入式闪存设备的方法。

    Semiconductor device structure and method for forming the same
    27.
    发明授权
    Semiconductor device structure and method for forming the same 有权
    半导体器件结构及其形成方法

    公开(公告)号：US09397228B2

    公开(公告)日：2016-07-19

    申请号：US14560353

    申请日：2014-12-04

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd

    发明人： Chang-Ming Wu ,  Wei-Hang Huang ,  Shih-Chang Liu

    IPC分类号： H01L21/3205 ,  H01L29/788 ,  H01L29/66

    CPC分类号： H01L29/66825 ,  H01L27/11531 ,  H01L29/42328

    摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The semiconductor device structure includes a second gate stack over the semiconductor substrate. The semiconductor device structure includes an erase gate between the first gate stack and the second gate stack. The erase gate has a recess recessed toward the semiconductor substrate. The semiconductor device structure includes a first word line adjacent to the first gate stack. The semiconductor device structure includes a second word line adjacent to the second gate stack.

    摘要翻译： 提供半导体器件结构。 半导体器件结构包括半导体衬底。 半导体器件结构包括半导体衬底上的第一栅极堆叠。 半导体器件结构包括半导体衬底上的第二栅极堆叠。 半导体器件结构包括在第一栅极堆叠和第二栅极堆叠之间的擦除栅极。 擦除栅极具有朝向半导体衬底凹陷的凹陷。 半导体器件结构包括与第一栅极堆叠相邻的第一字线。 半导体器件结构包括与第二栅极堆叠相邻的第二字线。

    BOUNDARY SCHEME FOR EMBEDDED POLY-SiON CMOS OR NVM IN HKMG CMOS TECHNOLOGY
    30.
    发明申请
    BOUNDARY SCHEME FOR EMBEDDED POLY-SiON CMOS OR NVM IN HKMG CMOS TECHNOLOGY 有权
    嵌入式POLY-SiON CMOS或NVM的HKMG CMOS技术的边界方案

    公开(公告)号：US20160181268A1

    公开(公告)日：2016-06-23

    申请号：US14580454

    申请日：2014-12-23

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Fang-Lan Chu

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11573 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11575 ,  H01L29/517 ,  H01L29/66545

    摘要： The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

    摘要翻译： 本公开涉及用于减少集成电路中的CMP凹陷的结构和方法。 在一些实施例中，该结构具有具有嵌入的存储区域和外围区域的半导体衬底。 在存储区域和外围区域之间形成一个或多个虚拟结构。 在嵌入的存储区域和外围区域之间的虚拟结构的放置使得其之间的沉积层的表面在抛光之后变得更平坦，而不会产生凹陷效应。 减少的凹陷减少金属残留物的形成，从而导致金属残留物导致的电流泄漏和短路。 此外，较少的凹陷将减少有源器件的多晶硅损耗。 在一些实施例中，虚拟结构之一形成有成角度的侧壁，其消除了对边界切割蚀刻工艺的需要。