摘要:
The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.
摘要:
A noise-removing circuit includes a first capacitor to charge a first voltage supplied to a first node during a first period in which a first switching control signal is supplied, a second capacitor to charge a second voltage supplied to a third node during the first period, a third capacitor to charge the first voltage during a second period in which a second switching control signal is supplied, and to charge the second voltage charged in the second capacitor as a third voltage during a third period in which a third switching control signal is supplied, a fourth capacitor to charge the second voltage during the second period, and to charge the first voltage charged in the first capacitor as a fourth voltage during the third period, and a differential amplifier to output a voltage difference between the third voltage and the fourth voltage.
摘要:
A charge domain filter (CDF) is provided. The CDF includes a switched-capacitor network (SCN) and a clock generator. An input of the SCN receives an input signal. The SCN samples the input signal according to clock signals with different phases. The clock generator is coupled to the SCN for providing the clock signals. The clock generator adjusts phase differences of the clock signals or pulse widths of the clock signals in accordance with a control signal.
摘要:
Operating capacitive sensors in force feedback mode has many benefits, such as improved bandwidth, and lower sensitivity to process and temperature variation. To overcome, the non-linearity of the voltage-to-force relation in capacitive feedback, a two-level feedback signal is often used. Therefore, a single-bit Σ-Δ modulator represents a practical way to implement capacitive sensors interface circuits. However, high-Q parasitic modes that exist in high-Q sensors (operating in vacuum) cause a stability problem for the Σ-Δ loop, and hence, limit the applicability of Σ-Δ technique to such sensors. A solution is provided that allows stabilizing the Σ-Δ loop, in the presence of high-Q parasitic modes. The solution is applicable to low or high order Σ-Δ based interfaces for capacitive sensors.
摘要:
An amplifier (1) includes an analogue-to-digital converter (ADC) (7) and a switched capacitor output stage (8). The ADC (7) converts an analogue signal into a digital signal containing a sequence of symbols. The switched capacitor output stage (8) charges and discharges a capacitor to produce charge pulses at an output (3). During discharge, switches selectively couple the capacitor to the output (3) in opposite directions to produce charge pulses of opposing polarity. The values of the symbols in the digital signal are used to decide the polarity of charge pulses. In this manner, amplification can be achieved without introducing a direct current (DC) component to the signal at the output (3).
摘要:
There is provided a filter circuit including a passive mixer circuit, and a passive switched capacitor circuit that is connected to a rear stage of the passive mixer and includes a flying capacitor. The passive mixer circuit generates a baseband signal by multiplying an input signal supplied from a predetermined signal source impedance by each local oscillation signal and outputs the baseband signal to the passive switched capacitor circuit, the passive switched capacitor circuit performs predetermined filtering on the baseband signal supplied from the passive mixer circuit and outputs the processed baseband signal, and a capacitance of the flying capacitor of the passive switched capacitor circuit is a capacitance by which input impedance of the passive mixer circuit is matched to the signal source impedance.
摘要:
A down conversion filter with a plurality of sampling capacitor, wherein at least one sampling capacitor is discharged in sampling phases or charge-summing phases of the other sampling capacitors.
摘要:
The invention relates to an electronic integrated amplifier for driving an acoustic transducer. The amplifier comprises two differential input terminals to receive an input signal and a first and a second output terminal to provide an output signal to the transducer. In addition, the amplifier comprises an operational amplifier having an input end including differential inputs and an output end operatively associated with the first and second output terminals. A pair of input resistors connect the two differential input terminals to two intermediate terminals, respectively. A pair of feedback resistors connect the first and second output terminals to the two intermediate terminals, respectively. The integrated amplifier also comprises means for high-pass filtering the input signal. Such filtering means is characterized in that it comprises an input element interposed between said intermediate terminals and the input end of the operational amplifier, and a feedback element connected between the input end and the output end of the same operational amplifier.
摘要:
A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period
摘要:
A filter is implemented as cascaded stages, and in at least one stage all resistances are implemented as double-sampled switched-capacitor circuits. In a variation, at least one resistance is implemented as a double-sampled switched-capacitor T-network. In a variation, in an integrator stage, a resistance is implemented as a transconductance, and the cutoff frequency of the integrator stage scales with a switching frequency of a DC-DC voltage converter.