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公开(公告)号：US20170279468A1
公开(公告)日：2017-09-28
申请号：US15460155
申请日：2017-03-15
申请人： SK Hynix Inc.
发明人： Naveen Kumar , Aman Bhatia , Yi-Min Lin
CPC分类号： H03M13/6502 , H03M13/152 , H03M13/2909 , H03M13/2942 , H03M13/2963 , H03M13/2978 , H03M13/453
摘要： A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.
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公开(公告)号：US09768805B2
公开(公告)日：2017-09-19
申请号：US14725706
申请日：2015-05-29
发明人： David C. Uliana , Newton G. Petersen , Tai A. Ly , Qing Ruan , James C. Nagle , Swapnil D. Mhaske , Hojin Kee , Adam T. Arnesen
CPC分类号： H03M13/1102 , H03M13/611 , H03M13/6502 , H03M13/6561 , H04L1/0057
摘要： Techniques relating to LDPC encoding. A set of operations is produced that is usable to generate an encoded message based on an input message. The set of operations corresponds to operations for entries in a smaller matrix representation that specifies locations of non-zero entries in an LDPC encoding matrix. A mobile device is configured with the set of operations to perform LDPC encoding. Circuitry configured with the set of operations performs LDPC encoding with high performance, relatively small area and/or low power consumption.
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公开(公告)号：US20170187390A1
公开(公告)日：2017-06-29
申请号：US15300269
申请日：2015-03-26
申请人： THOMSON LICENSING
发明人： Nicolas LE SCOUARNEC , Jean BOLOT , Brian ERIKSSON , Sebastien LASSERRE , Mark CROVELLA , Meinolf BILAWAT , Klaus GAEDKE , Jens PETER WITTENBURG , Christophe DIOT , Martin MAY
IPC分类号： H03M13/09 , G06F11/10 , H03M13/11 , C12Q1/68 , H03M13/29 , H03M13/00 , G06F19/28 , G06F3/06 , H03M13/15
CPC分类号： H03M13/09 , C12Q1/68 , C12Q1/6806 , G06F3/0619 , G06F3/064 , G06F3/065 , G06F3/0661 , G06F3/0673 , G06F11/1004 , G06F11/1076 , G06F19/10 , G06F19/28 , G06N3/123 , G11C13/02 , H03M13/1102 , H03M13/1515 , H03M13/154 , H03M13/2906 , H03M13/3761 , H03M13/6502 , C12Q2563/185
摘要： In one embodiment, it is proposed a method for storing input data on a set of DNA strands, said input data being represented in a numeral system. This method is remarkable in that it comprises: formatting said input data into a set of blocks of data, each block of data having a size inferior to a size of one DNA strand; applying a first encoding with an erasure code on said set of blocks of data, defining a first set of modified blocks of data, each modified block of data having a size inferior to a size of one DNA strand; applying a second encoding using an error correcting code on each modified block of data of said first set, defining a second set of modified blocks of data, each modified block having a size inferior to a size of one DNA strand; encoding each modified block of data of said second set into a nucleotides block sequence; generating a set of DNA strands, each DNA strand comprising a nucleotides block sequence obtained through said encoding.
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公开(公告)号：US20170177440A1
公开(公告)日：2017-06-22
申请号：US15451019
申请日：2017-03-06
申请人： AMPLIDATA N.V.
CPC分类号： G06F11/1092 , G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/067 , G06F11/1088 , G06F11/1662 , G06F11/2094 , G06F11/30 , G06F11/3034 , G06F11/3055 , H03M13/154 , H03M13/6502
摘要： A distributed object storage system has a monitoring agent and/or a maintenance agent configured to determine for each of a plurality of repair tasks the actual concurrent failure tolerance of a corresponding repair data object. The actual concurrent failure tolerance corresponds to the number of storage elements that store sub blocks of the repair data object and are allowed to fail concurrently.
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公开(公告)号：US20170163287A1
公开(公告)日：2017-06-08
申请号：US15434210
申请日：2017-02-16
CPC分类号： H03M13/1108 , G11B20/1833 , H03M13/1102 , H03M13/152 , H03M13/29 , H03M13/2906 , H03M13/6502
摘要： Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result. The decoder is configured to run up to a particular number of iterations to provide each of the results. A second ECC decoder is configured to decode a third codeword to provide decoded data, wherein the third codeword comprises the first result and the second result. An evaluation module is configured to initiate a recovery scheme responsive to the decoded data including an error.
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公开(公告)号：US20170153944A1
公开(公告)日：2017-06-01
申请号：US15363813
申请日：2016-11-29
发明人： Andrew D. Baptist , Greg R. Dhuse , Scott M. Horan , Ravi V. Khadiwala , Wesley B. Leggette , Manish Motwani , Jason K. Resch , Praveen Viraraghavan , Ilya Volvovski , Trevor J. Vossberg , Ethan S. Wozniak
CPC分类号： G06F3/067 , G06F3/0619 , G06F3/0629 , G06F3/064 , G06F3/0644 , G06F3/0665 , G06F3/0689 , G06F9/4881 , G06F9/5083 , G06F11/1076 , G06F11/1092 , G06F11/1402 , G06F11/1464 , G06F12/0866 , G06F12/0891 , G06F15/17331 , G06F2201/84 , G06F2211/1007 , G06F2212/1024 , G06F2212/154 , G06F2212/263 , G06F2212/403 , H03M13/1515 , H03M13/616 , H03M13/6502 , H04L61/1582 , H04L61/6004 , H04L63/101
摘要： A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device receives a data access request for a data object and determines a first revision number of a corresponding set of EDSs stored among first SU(s) and a second revision number of a corresponding trimmed copy of the set of EDSs stored among second SU(s). When the second revision number compares favorably to the first revision number, the computing device issues the data access request to the first SU(s) and/or the second SU(s) and issues the data access request for the data object to only the first SU(s) when it doesn't.
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公开(公告)号：US20170153942A1
公开(公告)日：2017-06-01
申请号：US15362615
申请日：2016-11-28
CPC分类号： G06F3/067 , G06F3/061 , G06F3/0619 , G06F3/0629 , G06F3/0635 , G06F3/064 , G06F3/0644 , G06F3/0665 , G06F3/0689 , G06F9/4881 , G06F9/5083 , G06F11/1076 , G06F11/1092 , G06F11/1402 , G06F11/1464 , G06F12/0866 , G06F12/0891 , G06F15/17331 , G06F2201/84 , G06F2211/1007 , G06F2212/1024 , G06F2212/154 , G06F2212/263 , G06F2212/403 , H03M13/1515 , H03M13/616 , H03M13/6502 , H04L61/1582 , H04L61/6004 , H04L63/101
摘要： A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device receives a data access request for an encoded data slice (EDS) associated with a data object. The computing device compares a slice name of the data access request with slice names stored within RAM. When the data access request slice name compares unfavorably with those stored slice names, the computing device transmits an empty data access response that includes no EDS to the other computing device without needing to access a hard disk drive (HDD) that stores EDSs. Alternatively, the computing device transmits a data access response that includes the EDS.
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公开(公告)号：US09660669B2
公开(公告)日：2017-05-23
申请号：US14580514
申请日：2014-12-23
发明人： Hong-sil Jeong , Sang-hyo Kim , Kyung-joong Kim , Se-ho Myung , Jong-hwan Kim , Dae-hyun Ryu , Min Jang
CPC分类号： H03M13/6502 , H03M13/1102 , H03M13/1148 , H03M13/1154 , H03M13/1197 , H03M13/611 , H03M13/616
摘要： An encoding apparatus which performs encoding such as Low Density Parity Check (LDPC) encoding is provided. The encoding apparatus includes: an encoder encoding input bits using a parity check matrix including a plurality of blocks, each being formed of a first information word sub-matrix and a first parity sub-matrix arranged next to each other, and a second information sub-matrix and a second parity sub-matrix arranged next to each other; a bit determiner determining a value of a last sub-parity bit among sub-parity bits generated by encoding the input bits with respect to a first block among the plurality of blocks; and a bit modifier reversing values of bits generated by encoding the input bits with respect to a second block next to the first block based on the value of the last parity bit among the sub-parity bits generated by the encoding with respect to the first block.
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公开(公告)号：US09602141B2
公开(公告)日：2017-03-21
申请号：US14257800
申请日：2014-04-21
发明人： Xinmiao Zhang , Ying Yu Tai
CPC分类号： H03M13/616 , G11C2029/0411 , H03M13/1102 , H03M13/1111 , H03M13/114 , H03M13/116 , H03M13/6502
摘要： High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.
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公开(公告)号：US20170077963A1
公开(公告)日：2017-03-16
申请号：US14852988
申请日：2015-09-14
发明人： Seong-Ook JUNG , Sara CHOI , Byungkyu SONG , Taehui NA , Jisu KIM , Jung Pill KIM , Sungryul KIM , Taehyun KIM , Seung Hyuk KANG
IPC分类号： H03M13/00
CPC分类号： H03M13/616 , G06F11/10 , G06F11/1012 , H03M13/152 , H03M13/1575 , H03M13/617 , H03M13/6502
摘要： Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.
摘要翻译： 错误检测和校正解码装置根据数据输入是否包含单位错误或多位错误，执行单错误纠正双重错误检测（SEC-DED）或双重纠错三重错误检测（DEC-TED） ，以减少单位错误时的功耗和延迟，并在多位错误的情况下提供强大的纠错。
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