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公开(公告)号：US10203911B2
公开(公告)日：2019-02-12
申请号：US15157982
申请日：2016-05-18
申请人： Friday Harbor LLC
摘要： A multi-processor system with a portion of content-addressable memory (CAM) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. However the system may control access to the tuple space so that no read operations may be performed for a particular tuple space before that space is written to. Further, no write operations may be performed to the tuple space prior to previous written data being read from the tuple space. A processor wishing to use the tuple space before being permitted to do so may be stalled, thus controlling data flow between operating processors.
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公开(公告)号：US10191839B2
公开(公告)日：2019-01-29
申请号：US15590081
申请日：2017-05-09
发明人： Takeo Miki
摘要： To provide a search device with less memory consumption, the search device includes a first associative memory searched with a first search key, a second associative memory searched with a second search key, a concatenated search data generating unit that generates first search information based on hit information including multiple hits in the first associative memory, and a search key generating unit that includes a first key generating unit generating a portion of search data as the first search key and a second search key generating unit generating the first search information and another portion of the search data as the second search key.
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公开(公告)号：US10141055B2
公开(公告)日：2018-11-27
申请号：US15841490
申请日：2017-12-14
摘要： Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
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公开(公告)号：US10127282B2
公开(公告)日：2018-11-13
申请号：US15305960
申请日：2014-04-30
发明人： Sheng Li , Kevin T. Lim , Dejan S. Milojicic , Paolo Faraboschi
摘要： A bit vector for a Bloom filter is determined by performing one or more hash function operations on a set of ternary content addressable memory (TCAM) words. A TCAM array is partitioned into a first portion to store the bit vector for the Bloom filter and a second portion to store the set of TCAM words. The TCAM array can be searched using a search word by performing the one or more hash function operations on the search word to generate a hashed search word and determining whether bits at specified positions of the hashed search word match bits at corresponding positions of the bit vector stored in the first portion of the TCAM array before searching the second portion of the TCAM array with the search word.
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公开(公告)号：US20180300267A1
公开(公告)日：2018-10-18
申请号：US15857519
申请日：2017-12-28
申请人： Netlist, Inc.
摘要： A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.
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公开(公告)号：US20180189585A1
公开(公告)日：2018-07-05
申请号：US15784065
申请日：2017-10-13
发明人： Guobiao ZHANG
IPC分类号： G06K9/00 , G06F21/56 , G06K9/62 , G11C13/00 , G11C15/00 , G11C17/10 , G11C17/16 , G11C5/02 , G11C5/06
CPC分类号： G06K9/00973 , G06F21/564 , G06F21/567 , G06F2221/032 , G06K9/62 , G11C5/025 , G11C5/063 , G11C7/1006 , G11C7/24 , G11C13/0002 , G11C13/003 , G11C15/00 , G11C15/04 , G11C17/10 , G11C17/165 , G11C2213/71
摘要： The present invention discloses a three-dimensional memory (3D-M) with in-situ anti-malware capabilities (3D-MAM). It comprises a plurality of storage-processing units (SPU). Each SPU comprises at least a 3D-M array for storing computer data and a pattern-processing circuit for screening the computer data against a malware pattern. The 3D-M array is stacked above the pattern-processing circuit. Multiple 3D-MAM dice can form a storage card, or a solid-state drive with in-situ anti-malware capabilities.
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公开(公告)号：US09947687B2
公开(公告)日：2018-04-17
申请号：US15176624
申请日：2016-06-08
发明人： Ferdinando Bedeschi
IPC分类号： G11C15/00 , H01L27/11597 , H01L29/78 , H01L27/1159 , H01L27/11587 , H01L29/423
CPC分类号： H01L27/11597 , H01L27/1157 , H01L27/11582 , H01L27/11587 , H01L27/1159 , H01L29/4238 , H01L29/42392 , H01L29/7827 , H01L29/78391
摘要： A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.
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公开(公告)号：US09934857B2
公开(公告)日：2018-04-03
申请号：US15228559
申请日：2016-08-04
发明人： Le Zheng , Brent Buchanan , John Paul Strachan
CPC分类号： G11C15/046
摘要： An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.
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公开(公告)号：US09905304B2
公开(公告)日：2018-02-27
申请号：US15000481
申请日：2016-01-19
申请人： SK hynix Inc.
发明人： Eun Young Park
CPC分类号： G11C16/32 , G11C15/00 , G11C16/0483 , G11C16/10 , G11C2211/5646
摘要： There are provided a memory system having improved reliability and an operating method thereof. A memory system includes a semiconductor memory device including a memory cell array having a plurality of pages, and a controller for sequentially transmitting, to the semiconductor memory device, physical block addresses of pages to be programmed among the plurality of pages. In the memory system, the semiconductor memory device selects a page corresponding to each of the physical block addresses among the plurality of pages according to previously stored program speed information, and performs a program operation on the selected page.
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公开(公告)号：US20170358332A1
公开(公告)日：2017-12-14
申请号：US15688545
申请日：2017-08-28
发明人： Troy A. Manning
IPC分类号： G11C7/06 , G11C7/10 , G11C15/00 , G06F12/00 , G11C11/4093 , G11C11/4096 , G11C11/4091 , G11C11/4094
CPC分类号： G11C7/065 , G06F12/00 , G11C7/1006 , G11C7/1051 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C15/00
摘要： The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
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