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    System and method for high speed packet transmission
    25.
    发明授权
    System and method for high speed packet transmission 有权
    高速数据包传输的系统和方法

    公开(公告)号：US09461940B2

    公开(公告)日：2016-10-04

    申请号：US14326859

    申请日：2014-07-09

    申请人： Foundry Networks, LLC

    发明人： Yuen Fai Wong

    IPC分类号： H04L12/28 ,  H04L12/931 ,  H04L12/46 ,  H04L12/743 ,  H04L12/935 ,  H04Q11/04 ,  H04L5/14 ,  H04L12/741

    CPC分类号： H04L49/352 ,  H04L5/14 ,  H04L12/4645 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/30 ,  H04L49/3063 ,  H04Q11/0428

    摘要： The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

    摘要翻译： 本发明提供了用于在一个或多个源设备与一个或多个目的地设备之间提供超过每秒10吉比特的数据传输速度的系统和方法。 根据一个实施例，本发明的系统包括第一和第二媒体访问控制（MAC）接口，以便于在相关联的一组物理接口上接收和传输分组。 该系统还考虑了耦合到MAC接口和相关联的第一和第二存储器结构的第一和第二现场可编程门阵列（FPGA），第一和第二FPGA被配置为执行从第一和第二MAC接口接收的分组的初始处理 并且调度分组到第一和第二MAC接口的传输以传输到一个或多个目的地设备。 第一和第二FPGA进一步操作以分派和从第一和第二存储器结构检索数据包。 耦合到第一和第二存储器结构和背板的第三FPGA可操作以从第一和第二存储器结构检索和分配分组，计算分组的适当目的地并组织用于传输的分组。 第三个FPGA进一步操作以从背板接收和分发分组。

    Relay device selection device, transmission system, and program for relay device selection device
    27.
    发明授权
    Relay device selection device, transmission system, and program for relay device selection device 有权
    中继设备选择设备，传输系统和中继设备选择设备程序

    公开(公告)号：US09438971B2

    公开(公告)日：2016-09-06

    申请号：US14398160

    申请日：2013-05-20

    申请人： Naoki Umehara

    发明人： Naoki Umehara

    IPC分类号： H04Q11/04 ,  H04B7/15 ,  H04W16/26

    CPC分类号： H04Q11/04 ,  H04B7/15 ,  H04Q2213/13191 ,  H04Q2213/1324 ,  H04Q2213/13389 ,  H04W16/26

    摘要： A selection device 80 outputs domain information that indicates a management system 50 capable of executing control associated with the start of communication using a selected relay device 30. Consequently, the control associated with the start of communication using the selected relay device 30 can be executed by any of the management systems 50 indicated by the domain information. That is, a load based on the control of the start of communication can be dispersed into a plurality of management systems 50, and thus there is an effect of reducing a load to the management systems 50.

    摘要翻译： 选择装置80输出指示能够使用所选择的中继装置30执行与通信开始相关联的控制的管理系统50的域信息。因此，与使用所选择的中继装置30的通信开始相关联的控制可以通过 由域信息指示的任何管理系统50。 也就是说，基于通信开始的控制的负载可以分散到多个管理系统50中，因此具有减少对管理系统50的负担的效果。

    Network element for switching time division multiplex signals
    30.
    发明授权
    Network element for switching time division multiplex signals 有权
    用于切换时分复用信号的网元

    公开(公告)号：US09380363B2

    公开(公告)日：2016-06-28

    申请号：US14237184

    申请日：2012-07-24

    申请人： Juergen Loehr

    发明人： Juergen Loehr

    IPC分类号： H04Q11/04 ,  H04L12/54 ,  H04L12/935 ,  H04L12/861 ,  H04L29/12 ,  H04L12/70

    CPC分类号： H04Q11/0457 ,  H04L12/5601 ,  H04L49/3081 ,  H04L49/9057 ,  H04L61/2069 ,  H04L2012/5626

    摘要： A network node, which is designed for switching of time-division multiplex signals; contains a number of line cards (LCI-LCn), a switch fabric (SF) interconnecting the line cards (LCI-LCn), and a control system (CS). The switching fabric (SF) is a cell based switch with one or more switch modules (SET-SEn) adapted to switch cells of a predefined cell format on the basis of addresses contained in cell headers of the cells. The line cards (LCI-LCn) have segmentation and reassembly devices (SARI-SARn) for segmenting input time-division multiplex signals into cells of the preformed cell format and adding address information to each cell and for reassembling cells received from said switch fabric (SF) into output time-division multiplex signals. The control system (CS) is connected to a switched port of the switch fabric (SF) and exchanges with the line cards (LCI-LCn) control and/or Operation, Administration and Maintenance (OAM) messages over the switch fabric (SF) using cells of the preformed cell format.

    摘要翻译： 一个网络节点，用于切换时分复用信号; 包含多个线路卡（LCI-LCn），互连线卡（LCI-LCn）和控制系统（CS）的交换结构（SF）。 交换结构（SF）是具有一个或多个交换模块（SET-SEn）的基于小区的交换机，其适于基于小区的小区头部中包含的地址来切换预定义小区格式的小区。 线路卡（LCI-LCn）具有分段和重组装置（SARI-SARn），用于将输入时分多路复用信号分割成预制小区格式的小区，并将地址信息添加到每个小区并重新组合从所述交换结构接收的小区（ SF）转换为输出时分复用信号。 控制系统（CS）连接到交换结构（SF）的交换端口，并通过交换结构（SF）与线路卡（LCI-LCn）控制和/或操作，管理和维护（OAM）消息进行交换， 使用预制细胞格式的细胞。