公开(公告)号：US20240427679A1

公开(公告)日：2024-12-26

申请号：US18756550

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Renu Patle ,  Hanmanthrao Patli ,  Rakesh Mehta ,  Hagay Spector ,  Ivan Herrera Mejia ,  Fylur Rahman Sathakathulla ,  Gowtham Raj Karnam ,  Mohsin Ali ,  Sahar Sharabi ,  Abraham Halevi Fraenkel ,  Eyal Pniel ,  Ehud Cohn ,  Raghav Ramesh Lakshmi ,  Altug Koker

IPC: G06F11/26 ,  G06F9/30

Abstract: Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.

公开(公告)号：US12177895B2

公开(公告)日：2024-12-24

申请号：US18194388

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Feng Jiang ,  Chittabrata Ghosh ,  Qinghua Li ,  Jonathan Segev ,  Ganesh Venkatesan

IPC: H04W72/04 ,  H04W4/02 ,  H04W24/10 ,  H04W64/00 ,  H04W72/0446 ,  H04W74/06

Abstract: This disclosure describes systems, methods, and devices related to uplink location measurement report (LMR) feedback. A device may perform availability window negotiation during a negotiation phase of a location determination associated with a first initiating device of one or more initiating devices. The device may determine a status of a first LMR associated with the first initiating device. The device may cause to send a polling request to one more initiating devices during a first availability window. The device may identify a polling response from at least one of the one or more initiating devices. The device may perform one or more sounding measurements with the at least one of the one or more initiating devices during a measurement phase. The device may cause to send a trigger frame to the at least one of the one or more initiating devices.

公开(公告)号：US12176643B2

公开(公告)日：2024-12-24

申请号：US17033386

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Thomas Boyd ,  Feifei Cheng ,  Eric W. Buddrius ,  Mohanraj Prabhugoud

IPC: H01R12/91 ,  H01R12/70 ,  H01R12/71 ,  H01R12/88 ,  H05K7/10

Abstract: Embodiments disclosed herein include sockets and electronic packages with socket architectures. In an embodiment, a socket comprises a housing with a first surface and a second surface. In an embodiment, a plurality of interconnect pins pass through the housing. In an embodiment, an alignment hole is provided through the housing. In an embodiment, an alignment post extending out from the first surface of the housing is also provided.

公开(公告)号：US12176292B2

公开(公告)日：2024-12-24

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US12176147B2

公开(公告)日：2024-12-24

申请号：US17357385

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： James D. Waldemer ,  Matthieu Giraud-Carrier ,  Bernhard Sell ,  Travis W. Lajoie ,  Wilfred Gomes ,  Abhishek A. Sharma

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/40

Abstract: Disclosed herein are IC structures with three-dimensional capacitors with double metal electrodes provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example three-dimensional capacitor includes first and second capacitor electrodes and a capacitor insulator between them. Each capacitor electrode includes a planar portion extending across the support structure and one or more via portions extending into one or more via openings in the support structure. The capacitor insulator also includes a planar portion and a via portion extending into the via opening(s). The planar portion of the capacitor electrodes are thicker than the via portions. Each capacitor electrode may be deposited using two deposition processes, such as a conformal deposition process for depositing the via portion of the electrode, and a sputter process for depositing the planar portion of the electrode.

公开(公告)号：US12174911B2

公开(公告)日：2024-12-24

申请号：US17133473

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Menachem Adelman ,  Robert Valentine ,  Daniel Towner ,  Amit Gradstein ,  Mark Jay Charney

IPC: G06F17/16

Abstract: An apparatus and method for complex matrix multiplication. For example, one embodiment of a processor comprises: a decoder to decode a first complex matrix multiplication instruction; execution circuitry to execute the first complex matrix multiplication instruction, the execution circuitry comprising parallel multiplication circuitry to multiply real values from the first plurality of real and imaginary values with corresponding real values from the second plurality of real and imaginary values to generate a first plurality of real products, to multiply imaginary values from the first plurality of real and imaginary values with corresponding imaginary values from the second plurality of real and imaginary values to generate a second plurality of real products; and addition/subtraction circuitry to subtract each real product in the second plurality of real products from a corresponding real product in the first plurality of real products to produce a corresponding real value in the result matrix. The decoder may also decode and the execution circuitry may execute a second complex matrix multiplication instruction to multiply real and imaginary values from the first plurality with corresponding imaginary and real values, respectively, from the second plurality to generate first and second pluralities of imaginary products, and to add corresponding imaginary products to produce a corresponding imaginary value in the result matrix.

公开(公告)号：US20240422819A1

公开(公告)日：2024-12-19

申请号：US18814205

申请日：2024-08-23

Applicant: Intel Corporation

Inventor： Laurent CARIOU ,  Thomas J. KENNEY

IPC: H04W74/0808

Abstract: This disclosure describes systems, methods, and devices related to prioritized access. A device may broadcast advertisements to stations (STAs) indicating specific service periods for prioritized channel access within a Basic Service Set (BSS). The device may send an indication to the STAs queued for prioritized access to transmit reservation signals at a predetermined time post a start of a contention period. The device may send contention window (CW) parameter settings to the STAs to control their backoff counter values during periods of prioritized access contention. The device may detect reception of overlapping reservation signals from STAs and enforce clear channel assessment (CCA) protocol to cause STAs to defer their transmissions.

公开(公告)号：US20240421025A1

公开(公告)日：2024-12-19

申请号：US18290289

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Lianchang DU ,  Jeffory L. SMALLEY ,  Srikant NEKKANTY ,  Eric W. BUDDRIUS ,  Yi ZENG ,  Xinjun ZHANG ,  Maoxin YIN ,  Zhichao ZHANG ,  Chen ZHANG ,  Yuehong FAN ,  Mingli ZHOU ,  Guoliang YING ,  Yinglei REN ,  Chong J. ZHAO ,  Jun LU ,  Kai WANG ,  Timothy Glen HANNA ,  Vijaya K. BODDU ,  Mark A. SCHMISSEUR ,  Lijuan FENG

IPC: H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01R13/627

Abstract: A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.

公开(公告)号：US20240420274A1

公开(公告)日：2024-12-19

申请号：US18336821

申请日：2023-06-16

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  James Valerio

IPC: G06T1/20

Abstract: Described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. The performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. In one embodiment, performance monitoring for the separate workloads can be configured, for example, by filtering based on the respective shader programs, fixed function units, and/or processing resources used to execute the workloads.

公开(公告)号：US20240418825A1

公开(公告)日：2024-12-19

申请号：US18664048

申请日：2024-05-14

Applicant: INTEL CORPORATION

Inventor： Ofer Markish ,  Ophir Shabtay ,  Thushara Hewavithana ,  Arnaud Amadjikpe ,  Shengbo Xu

IPC: G01S7/35 ,  B60W60/00 ,  G01S13/89 ,  H01Q1/32 ,  H01Q21/22

Abstract: Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) antennas to transmit radar Tx signals, and a plurality of Receive (Rx) antennas to receive radar Rx signals. For example, the radar Rx signals may be based on the radar Tx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. In other aspects, the apparatus may include any other additional or alternative elements and/or may be implemented as part of any other device.