公开(公告)号：US5365193A

公开(公告)日：1994-11-15

申请号：US982376

申请日：1992-11-25

Applicant: Maurizio Zuffada ,  Gianfranco Vai ,  Marco Gregori ,  David Moloney ,  Giorgio Betti

Inventor： Maurizio Zuffada ,  Gianfranco Vai ,  Marco Gregori ,  David Moloney ,  Giorgio Betti

IPC: H03F1/22 ,  H03F1/30 ,  H03F3/34 ,  H03F3/45

CPC classification number: H03F3/4508 ,  H03F1/223 ,  H03F3/45286 ,  H03F2203/45304 ,  H03F2203/45674 ,  H03F2203/45696

Abstract: A circuit device for neutralizing thermal drift in a transconductor differential stage using a first circuit portion which corresponds structurally to the transconductor differential stage and has a pair of MOS input transistors defining a transconductance value which is substantially proportional to that of the transconductor differential stage, a pair of bipolar output transistors coupled to the MOS input transistors in a cascode configuration, and a second circuit portion being supplied a current from an output of the first differential portion to thereby output a current to be passed to the transconductor differential stage. The value of the output current is inversely proportional to temperature-dependent parameters of the transconductance.

Abstract translation: 一种电路装置，用于使用在结构上对应于跨导差分级的第一电路部分中和跨导差分级中的热漂移，并且具有一对限定跨导值的MOS输入晶体管，所述跨导值基本上与跨导差动级的导数值成正比， 一对双极性输出晶体管，其以共源共栅配置耦合到MOS输入晶体管;以及第二电路部分，从第一差分部分的输出端提供电流，从而输出要传递到跨导差分级的电流。 输出电流的值与跨导的温度相关参数成反比。

公开(公告)号：US5353194A

公开(公告)日：1994-10-04

申请号：US142723

申请日：1993-10-24

Applicant: Giuseppe Libretti ,  Paolo Casati

Inventor： Giuseppe Libretti ,  Paolo Casati

IPC: H01L25/07 ,  H01L23/14 ,  H01L25/065 ,  H01L25/18 ,  H05K7/20

CPC classification number: H01L23/142 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2224/48227

Abstract: A modular construction power circuit arrangement is disclosed which comprises a thin metal plate performing holder and heat sink functions, a multiplicity of electronic devices in the form of semiconductor material chips having metalized pads as their terminals, a printed circuit board attached to the thin metal plate, electric conductors between the metalized pads and the printed circuit on the board, terminating connectors which form a part of the printed circuit board for connecting the circuit arrangement to external circuits, and a plastics material body which conglomerates a portion of the thin metal plate, the semiconductor material chips, and the printed circuit board. At least one of the semiconductor material chips is attached directly to the thin metal plate and extends therefrom through an opening in the printed circuit board.

Abstract translation: 公开了一种模块化结构电力电路装置，其包括执行保持器和散热器功能的薄金属板，具有金属化焊盘作为其端子的半导体材料芯片形式的多个电子器件，附接到薄金属板的印刷电路板 ，金属化焊盘与板上的印刷电路之间的电导体，形成用于将电路装置连接到外部电路的印刷电路板的一部分的终端连接器以及聚集薄金属板的一部分的塑料材料体， 半导体材料芯片和印刷电路板。 半导体材料芯片中的至少一个直接附接到薄金属板，并从其穿过印刷电路板的开口延伸。

公开(公告)号：US5350998A

公开(公告)日：1994-09-27

申请号：US872462

申请日：1992-04-23

Applicant: Fabio Marchio ,  Enrico Novarini ,  Giorgio Rossi

Inventor： Fabio Marchio ,  Enrico Novarini ,  Giorgio Rossi

IPC: G05F3/22 ,  G05F3/30 ,  H03F1/30 ,  G05F3/16

CPC classification number: H03F1/302 ,  G05F3/225 ,  G05F3/30 ,  Y10S323/907

Abstract: A circuit for temperature compensating the inverse saturation current of a bipolar transistor having a collector region, base and emitter regions defining a base-emitter junction is disclosed. A diode element having substantially said same saturation current is parallel-connected in reverse configuration to said base-emitter junction of the bipolar transistor. If the bipolar transistor is NPN type, the diode has an anode and cathode connected respective to the emitter and base regions of the transistor.

Abstract translation: 公开了一种用于温度补偿具有限定基极 - 发射极结的集电极区域，基极和发射极区域的双极晶体管的逆饱和电流的电路。 具有基本上相同饱和电流的二极管元件以双向晶体管的基极 - 发射极的反向配置并联连接。 如果双极晶体管为NPN型，二极管的阳极和阴极分别连接晶体管的发射极和基极区域。

公开(公告)号：US5347493A

公开(公告)日：1994-09-13

申请号：US938731

申请日：1992-08-31

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C17/18 ,  G11C8/10 ,  G11C17/12 ,  G11C8/00

CPC classification number: G11C17/123 ,  G11C17/12 ,  G11C8/10

Abstract: A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection circuits driven through five buses for implementing a two-level decoding, thus driving less than all of the rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.

Abstract translation: 用于组合在可选择的NAND小区中的ROM矩阵的解码器利用通过五个总线驱动的四个选择电路来实现两级解码，从而通过多个可选驱动器驱动小于所有行。 行解码器的架构基于对多个行驱动器的细分，使得电路与由单元的特别小间距施加的几何约束物理上兼容。 与现有技术的解码器配备的存储器相比，行驱动器的细分对存取时间，可靠性和整体性能也具有积极的影响，并行驱动所有可选择的NAND包细胞的所有同行。

公开(公告)号：US5345417A

公开(公告)日：1994-09-06

申请号：US016741

申请日：1993-02-11

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: An integrated EPROM device which can be manufactured using standard high-definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line" formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

Abstract translation: 可以使用标准高清晰度光刻技术制造的集成EPROM器件，其具有与现有技术可以实现的最小尺寸相比具有明显减小的尺寸的单元电池，具有沿着阵列行的相邻单元之间的场隔离结构 连续隔离带的形式，其延伸到阵列的整个列长度，从而避免与光刻定义矩形几何相关的问题。 通过在两个相邻的栅极线之间形成的特殊的金属源“线”来实现每一行的电池单元之间的电互连，为了这个目的，为了共同沉积的金属层，漏极接触和这些源互连金属“ 线条“以自对准方式创建。

公开(公告)号：US5343068A

公开(公告)日：1994-08-30

申请号：US852310

申请日：1992-03-18

Applicant: Ferruccio Frisina ,  Giuseppe Ferla

Inventor： Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L29/73 ,  H01L21/22 ,  H01L21/322 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861 ,  H02L27/082 ,  H02L27/102 ,  H02L29/70

CPC classification number: H01L27/0761 ,  H01L21/221 ,  Y10S438/904

Abstract: A bipolar power device and a fast diode are formed in a single chip of semiconductor material. The chip contains a first area having high minority carrier lifetimes in which the bipolar power device is formed. The bipolar power device is therefore capable of handling high current densities. At least one second area of the device is formed with reduced minority carrier lifetimes, with a fast diode being formed in this region.

Abstract translation: 在单芯片半导体材料中形成双极功率器件和快速二极管。 芯片包含形成双极型功率器件的少数载流子寿命的第一区域。 因此，双极型功率器件能够处理高电流密度。 器件的至少一个第二区域形成为具有减少的少数载流子寿命，其中在该区域中形成快速二极管。

公开(公告)号：US5341282A

公开(公告)日：1994-08-23

申请号：US865421

申请日：1992-04-08

Applicant: Massimiliano Brambilla ,  Giampietro Maggioni

Inventor： Massimiliano Brambilla ,  Giampietro Maggioni

IPC: G01R31/02 ,  H01H47/32 ,  H02H3/08 ,  H02H9/04 ,  G05F1/573

CPC classification number: H01H47/325 ,  H02H3/08 ,  H02H9/047 ,  Y10T307/878

Abstract: An inductive load drive device which has a switch defining an output terminal connectable to an inductive load between the output terminal and a reference potential line is provided. A first current recirculating branch is connectable parallel to the load and a control opens and closes the switch so that the load is supplied with current rising to a first predetermined value in a first increasing phase and falling to a second predetermined value in a first recirculating phase. The device detects a short-circuit between the output terminal of the control device and the reference potential line with a first current sensor for detecting current flow in the first recirculating branch during the first recirculating phase. A fault signaling circuit connected to the first current sensor produces a short-circuit signal in the absence of current in the first recirculating branch during the first recirculating phase.

Abstract translation: 提供一种感性负载驱动装置，其具有限定可连接到输出端子和参考电位线之间的感性负载的输出端子的开关。 第一电流循环分支可平行于负载连接，并且控制器打开和闭合开关，使得负载在第一增加阶段中以上升到第一预定值并在第一再循环阶段中下降到第二预定值 。 该装置利用第一电​​流传感器检测控制装置的输出端与参考电位线之间的短路，用于检测在第一再循环阶段期间第一再循环分支中的电流。 连接到第一电流传感器的故障信号电路在第一再循环阶段期间在第一再循环分支中没有电流时产生短路信号。

公开(公告)号：US5338971A

公开(公告)日：1994-08-16

申请号：US982314

申请日：1992-11-27

Applicant: Paolo Casati ,  Marziano Corno ,  Giuseppe Marchisi

Inventor： Paolo Casati ,  Marziano Corno ,  Giuseppe Marchisi

IPC: H01L21/60 ,  H01L23/28 ,  H01L23/29 ,  H01L23/433 ,  H01L23/495 ,  H01L23/50 ,  H01L23/48 ,  H01L23/02 ,  H01L23/44 ,  H01L23/52

CPC classification number: H01L24/49 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49579 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85207 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/14 ,  H01L2924/181

Abstract: An electronic device structure which comprises a metal plate, a semiconductor material chip attached to the plate, terminal leads, interconnection wires between the leads and metallized regions of the chip, and a plastic body which encapsulates the whole with the exception of a surface of the plate and part of the leads. This structure has highly reliable means of electrical connection between at least one metallized region and the metal plate which comprise at least one metal beam resting onto the plate and being attached thereto by studs integral with the plate, and at least one wire welded between a metallized region of the chip and the metal beam between the studs. At least a portion of the beam and its connection wire are encapsulated within the plastics body.

Abstract translation: 一种电子器件结构，其包括金属板，附着到所述板的半导体材料芯片，端子引线，所述芯片的引线和金属化区域之间的互连线，以及除了所述芯片的表面之外的封装整体的塑料体 板和部分引线。 该结构具有至少一个金属化区域和金属板之间的电连接的高度可靠的装置，该金属板包括至少一个搁置在板上的金属梁，并且通过与该板一体的螺栓与其连接，以及至少一根焊接在金属化 芯片的区域和螺柱之间的金属梁。 梁和其连接线的至少一部分被封装在塑料体内。

公开(公告)号：US5300805A

公开(公告)日：1994-04-05

申请号：US85314

申请日：1993-06-29

Applicant: Marco Demicheli ,  Alberto Gola

Inventor： Marco Demicheli ,  Alberto Gola

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

CPC classification number: H01L27/0248

Abstract: A bias structure for an integrated circuit including first and second transistors having emitter terminals coupled respectively to the supply and to a terminal of a resistor whose potential, under certain operating conditions of the circuit, exceeds the supply voltage; base terminals connected to each other and to a current source; and collector terminals connected electrically (12) to an epitaxial tub housing the resistor. A resistor is preferably provided between the two collectors, so that, when the potential of the terminal of the resistor exceeds the supply voltage, the second transistor saturates and maintains the epitaxial tub of the resistor at a potential close to that of the resistor terminal, thus preventing the parasitic diode formed between the resistor and the epitaxial tub from being switched on.

Abstract translation: 一种用于集成电路的偏置结构，包括具有发射极端子的第一和第二晶体管，发射极端子分别耦合到电阻器和电阻器的端子，其电位在电路的某些工作条件下超过电源电压; 基端子彼此连接并连接到电流源; 和集电极端子（12）连接到容纳电阻器的外延阱。 优选地，在两个集电极之间设置电阻器，使得当电阻器的端子的电位超过电源电压时，第二晶体管将电阻器的外延阱饱和并保持在接近电阻器端子的电位， 从而防止形成在电阻器和外延槽之间的寄生二极管接通。

公开(公告)号：US5282161A

公开(公告)日：1994-01-25

申请号：US816885

申请日：1991-12-31

Applicant: Nuccio Villa

Inventor： Nuccio Villa

IPC: G11C16/04 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C11/34 ,  G11C11/40

CPC classification number: G11C16/0441 ,  H01L27/115 ,  H01L27/11526 ,  H01L29/7883 ,  H01L27/105

Abstract: An EEPROM cell with a single level gate structure is structured over at least three distinct active areas of the semiconducting substrate over which extend portions of the single isolated gate structure of the cell. A read transistor of the cell is formed in a distinct active area which is substantially isolated from the active area of the select transistor, wherein the thin dielectric tunnel layer is formed. Therefore the interface toward the external logic circuitry represented by the read transistor and the interface toward the programming circuitry are substantially isolated from each other. The read transistor may be designated to function at voltage and current levels compatible with the operating levels of the logic circuitry without interfering with the programming of the cell, thus eliminating the need for level regenerating stages. A second complementary read transistor may be formed into a fourth distinct active area, suitably doped, thus providing a read interface structured as a normal CMOS inverter stage.The ability of the read transistor to operate at standard CMOS levels, makes the EEPROM cell particularly suited for implementing multiplexing or programmable interconnection arrays in CMOS devices.

Abstract translation: 具有单电平栅极结构的EEPROM单元被构造在半导体衬底的至少三个不同的有效区域上，在单元隔离门结构的一部分上延伸。 单元的读取晶体管形成在与选择晶体管的有源区基本上隔离的不同有源区域中，其中形成有薄介质隧道层。 因此，由读取晶体管和向编程电路接口的外部逻辑电路的接口基本上彼此隔离。 读取晶体管可以被指定为在与逻辑电路的操作电平兼容的电压和电流水平下起作用，而不会干扰电池的编程，因此消除了对电平再生级的需要。 第二互补读取晶体管可以形成为适当地掺杂的第四不同的有效区域，从而提供构造为正常CMOS反相器级的读取界面。 读取晶体管以标准CMOS电平工作的能力使得EEPROM单元特别适合于在CMOS器件中实现复用或可编程互连阵列。