公开(公告)号：US20150171963A1

公开(公告)日：2015-06-18

申请号：US14599833

申请日：2015-01-19

Applicant: INPHI CORPORATION

Inventor： Sudeep BHOJA ,  Chao XU ,  Hari SHANKAR

IPC: H04B10/2575 ,  H04B10/50 ,  H04B10/27

CPC classification number: H04B10/2575 ,  H04B10/2507 ,  H04B10/27 ,  H04B10/40 ,  H04B10/50 ,  H04B10/503 ,  H04B10/5161 ,  H04B10/564 ,  H04B10/695 ,  H04L1/0041 ,  H04L7/0331

Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. A feedback mechanism is provided for adjusting the transmission power levels. There are other embodiments as well.

Abstract translation: 本发明涉及数据通信系统和方法。 更具体地，本发明的各种实施例提供一种通信接口，其被配置为通过光通信网络使用PAM格式在高带宽上传送数据。 提供了一种用于调整发射功率电平的反馈机制。 还有其它实施例。

公开(公告)号：US20150155946A1

公开(公告)日：2015-06-04

申请号：US14615626

申请日：2015-02-06

Applicant: INPHI CORPORATION

Inventor： Tom Peter Edward BROEKAERT ,  Hari SHANKAR

IPC: H04B10/54 ,  H04B10/524 ,  H04B10/27 ,  H04L7/00

CPC classification number: H04B10/5161 ,  H04B10/27 ,  H04B10/272 ,  H04B10/40 ,  H04B10/524 ,  H04B10/541 ,  H04B10/5561 ,  H04L7/0075

Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. In various embodiments, amplitude and phase of the optical wave are modulated. There are other embodiments as well.

Abstract translation: 本发明涉及数据通信系统和方法。 更具体地，本发明的各种实施例提供一种通信接口，其被配置为通过光通信网络使用PAM格式在高带宽上传送数据。 在各种实施例中，调制光波的振幅和相位。 还有其它实施例。

公开(公告)号：US09020346B2

公开(公告)日：2015-04-28

申请号：US13791201

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： Sudeep Bhoja

IPC: H04B10/272 ,  H04B10/40 ,  H04J14/00 ,  G02B6/26 ,  H04B10/54

CPC classification number: H04B10/272 ,  H04B10/40 ,  H04B10/541 ,  H04B14/023

Abstract: The present invention is directed to communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using PAM format(s) over optical communication networks. In certain embodiments, the communication interface is used by various devices within a spine-leaf network architecture, which allows large amount of data to be shared among servers.

Abstract translation: 本发明涉及通信系统和方法。 更具体地，本发明的各种实施例提供一种通信接口，其被配置为通过光通信网络使用PAM格式在高带宽上传送数据。 在某些实施例中，通信接口由脊叶网络架构内的各种设备使用，这允许在服务器之间共享大量的数据。

公开(公告)号：US08996960B1

公开(公告)日：2015-03-31

申请号：US13797583

申请日：2013-03-12

Applicant: Inphi Corporation

Inventor： Nirmal Raj Saxena ,  David Wang ,  Hamid Rategh ,  Lawrence Tse

IPC: G11C29/00 ,  H03M13/17

CPC classification number: H03M13/17 ,  G06F11/1048

Abstract: Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.

Abstract translation: 操作DIMM装置的技术。 该装置包括从0到N-1编号的多个DRAM器件，其中N是大于7（7）的整数，每个DRAM器件被配置在衬底模块中; 包括从0到N-1编号的多个数据缓冲器（DB）的缓冲器集成电路器件，其中N是大于7（7）的整数，每个数据缓冲器对应于一个DRAM器件; 以及与多个DRAM设备相关联的多个纠错模块（“ECM”）。

公开(公告)号：US08990491B1

公开(公告)日：2015-03-24

申请号：US13909489

申请日：2013-06-04

Applicant: Inphi Corporation

Inventor： Chao Xu

IPC: G06F12/00 ,  G11C7/10 ,  G11C5/10 ,  G06F11/27

CPC classification number: G11C7/1072 ,  G06F11/27 ,  G11C5/10 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C2207/2254

Abstract: Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a middle point, a left point, and a right point. The start point is a beginning of an eye opening at a reference voltage. The end point is at an ending of eye opening at the reference voltage. The middle point is at a center point of eye opening at the reference voltage. The left point is a left sampling location characterized by a minimum setup time requirement, and the right point is a right sampling location characterized by a minimum hold time requirement. Determining the points is based on shifting a DQS position and a DQ position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

Abstract translation: 用于处理来自高速通信总线的信号信息的技术。 这些技术包括确定以起点，终点，中点，左点和右点为特征的眼睛上的空间区域。 起始点是在参考电压下开眼的开始。 终点是在参考电压下的眼睛开度的结束。 中点位于参考电压下眼睛开口的中心点。 左点是以最小建立时间要求为特征的左采样位置，右点是以最小保持时间要求为特征的右采样位置。 确定点是基于移动DQS位置和DQ位置并运行多个内存自检（BIST）引擎和多个BIST测试结果。

公开(公告)号：US08949473B1

公开(公告)日：2015-02-03

申请号：US13768986

申请日：2013-02-15

Applicant: Inphi Corporation

Inventor： Christopher Haywood ,  Chao Xu ,  Fouad G. Tamer

IPC: G06F3/00 ,  G06F13/00 ,  H05K7/14 ,  G11C8/00

CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

Abstract translation: 本发明涉及服务器系统及其方法。 更具体地，本发明的实施例提供了服务器系统内的存储器控​​制器，其中存储器控制器可分离地连接到一个或多个处理器，多个易失性存储器模块和多个固态存储器模块。 该存储器控制器可以连接到其他类似配置的存储器控​​制器。 可以移除和/或更换易失性和固态存储器模块。 还有其它实施例。

公开(公告)号：US20150023398A1

公开(公告)日：2015-01-22

申请号：US14508586

申请日：2014-10-07

Applicant: INPHI CORPORATION

Inventor： Guojun REN ,  Karthik S. GOPALAKRISHNAN

IPC: H04B3/30 ,  H04L25/06

CPC classification number: H04B3/30 ,  G05F1/10 ,  H04L25/06

Abstract: The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source. The second gate is coupled to a fast node, and the second drain is coupled to the regulator output.

Abstract translation: 电压调节器装置具有宽带放大器，其具有输入参考电压Vref和输入反馈电压Vfbk。 该器件具有耦合到宽带放大器的源极跟随器，源极跟随器耦合到宽带放大器的输出。 器件具有VDD源，稳压器输出和耦合到源极跟随器和VDD源的电流源。 该器件具有包括第一晶体管的低频路径。 第一晶体管具有第一栅极，第一源极和第一漏极。 第一个源极耦合到VDD源。 第一栅极耦合到慢节点，第一漏极耦合到调节器输出端。 低频路径包括RC网络，其具有电容器，电阻器和配置在电阻器和电容器之间的慢节点。 该器件具有包括第二晶体管的高频路径。 第二晶体管具有第二栅极，第二源极和第二漏极。 第二个源极耦合到VDD源。 第二栅极耦合到快节点，第二漏极耦合到调节器输出。

公开(公告)号：US08901977B1

公开(公告)日：2014-12-02

申请号：US14321602

申请日：2014-07-01

Applicant: Inphi Corporation

Inventor： Guojun Ren

IPC: H03L7/06 ,  H03L7/08

CPC classification number: H03K5/14 ,  H02M3/07 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/0898

Abstract: The present invention is directed to signal processing system and electrical circuits. More specifically, embodiments of the present invention provide a DLL system that provides phase correction by determining a system offset based on phase differences among the delay lines. The offset is used as a part of a feedback loop to provide phase corrections for the delay lines. There are other embodiments as well.

Abstract translation: 本发明涉及信号处理系统和电路。 更具体地，本发明的实施例提供一种DLL系统，其通过基于延迟线之间的相位差确定系统偏移来提供相位校正。 偏移量用作反馈回路的一部分，为延迟线提供相位校正。 还有其它实施例。

公开(公告)号：US08885766B2

公开(公告)日：2014-11-11

申请号：US13952402

申请日：2013-07-26

Applicant: Inphi Corporation

Inventor： Jamal Riani ,  Sudeep Bhoja

IPC: H04L27/36 ,  H04L27/34

CPC classification number: H04B10/27 ,  H03K9/02 ,  H04B10/2504 ,  H04B10/61 ,  H04B14/004 ,  H04L27/02 ,  H04L27/06 ,  H04L27/34

Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using nDSQ format(s) over optical communication networks. In certain embodiments, the communication interface is used by various devices, such as spine switches and leaf switches, within a spine-leaf network architecture, which allows large amount of data to be shared among servers.

Abstract translation: 本发明涉及数据通信系统和方法。 更具体地，本发明的各种实施例提供了一种通信接口，其被配置为通过光通信网络使用nDSQ格式传输高带宽的数据。 在某些实施例中，通信接口由脊椎叶网络架构内的各种设备使用，例如脊柱交换机和叶片交换机，其允许在服务器之间共享大量的数据。

公开(公告)号：US08885691B1

公开(公告)日：2014-11-11

申请号：US13775041

申请日：2013-02-22

Applicant: Inphi Corporation

Inventor： Guojun Ren ,  Karthik S. Gopalakrishnan

IPC: H04B1/38 ,  H04L5/16 ,  G05F1/10 ,  H04B3/30

CPC classification number: H04B3/30 ,  G05F1/10 ,  H04L25/06

Abstract: The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source. The second gate is coupled to a fast node, and the second drain is coupled to the regulator output.

Abstract translation: 电压调节器装置具有宽带放大器，其具有输入参考电压Vref和输入反馈电压Vfbk。 该器件具有耦合到宽带放大器的源极跟随器，源极跟随器耦合到宽带放大器的输出。 器件具有VDD源，稳压器输出和耦合到源极跟随器和VDD源的电流源。 该器件具有包括第一晶体管的低频路径。 第一晶体管具有第一栅极，第一源极和第一漏极。 第一个源极耦合到VDD源。 第一栅极耦合到慢节点，第一漏极耦合到调节器输出端。 低频路径包括RC网络，其具有电容器，电阻器和配置在电阻器和电容器之间的慢节点。 该器件具有包括第二晶体管的高频路径。 第二晶体管具有第二栅极，第二源极和第二漏极。 第二个源极耦合到VDD源。 第二栅极耦合到快节点，第二漏极耦合到调节器输出。