中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.013 seconds)

    Memory buffer with data scrambling and error correction
    1.
    发明授权
    Memory buffer with data scrambling and error correction 有权
    具有数据加扰和纠错的存储缓冲器

    公开(公告)号：US09170878B2

    公开(公告)日：2015-10-27

    申请号：US13791124

    申请日：2013-03-08

    Applicant: Inphi Corporation

    Inventor： Christopher Haywood ,  David Wang

    IPC: G06F11/10 ,  G11C7/10 ,  G06F11/07 ,  G11C29/04

    CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

    Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

    Abstract translation: 一种用于操作DRAM设备的方法。 该方法包括在由计算系统托管的第一存储器模块中的存储器缓冲器中接收从计算系统的主机控制器存储在第一存储器模块的RAM中的数据的请求。 该方法包括响应于该请求而与RAM相关联的数据与存储缓冲器一起接收，响应于伪随机过程将该数据转换成加扰数据。 该方法包括利用存储缓冲器启动加扰数据到接口设备中。

    Memory buffer with one or more auxiliary interfaces
    2.
    发明授权
    Memory buffer with one or more auxiliary interfaces 有权
    具有一个或多个辅助接口的内存缓冲区

    公开(公告)号：US09323458B2

    公开(公告)日：2016-04-26

    申请号：US14665968

    申请日：2015-03-23

    Applicant: INPHI CORPORATION

    Inventor： Christopher Haywood

    IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

    CPC classification number: G06F3/0626 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/06 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C14/0045

    Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.

    Abstract translation: 本存储器系统包括存储器缓冲器，其具有被布置为缓冲由主机控制器写入或存储在DIMM上的RAM芯片的数据和/或命令字节的接口。 存储器缓冲器还包括至少一个额外的接口，其布置成在主机控制器或RAM芯片与耦合到至少一个附加接口的一个或多个外部设备之间缓冲数据和/或命令字节。 例如，存储器缓冲器可以包括SATA接口，并且被布置成在主机控制器或RAM芯片与耦合到SATA接口的闪存设备之间传送数据。 存储器缓冲器可以用于各种类型的系统，例如计算机服务器系统，网络系统或数据中心。

    Hybrid memory blade
    4.
    发明授权
    Hybrid memory blade 有权
    混合内存刀片

    公开(公告)号：US08949473B1

    公开(公告)日：2015-02-03

    申请号：US13768986

    申请日：2013-02-15

    Applicant: Inphi Corporation

    Inventor： Christopher Haywood ,  Chao Xu ,  Fouad G. Tamer

    IPC: G06F3/00 ,  G06F13/00 ,  H05K7/14 ,  G11C8/00

    CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

    Abstract translation: 本发明涉及服务器系统及其方法。 更具体地，本发明的实施例提供了服务器系统内的存储器控​​制器，其中存储器控制器可分离地连接到一个或多个处理器，多个易失性存储器模块和多个固态存储器模块。 该存储器控制器可以连接到其他类似配置的存储器控​​制器。 可以移除和/或更换易失性和固态存储器模块。 还有其它实施例。

    Hybrid memory blade
    5.
    发明授权
    Hybrid memory blade 有权
    混合内存刀片

    公开(公告)号：US09547610B2

    公开(公告)日：2017-01-17

    申请号：US15073947

    申请日：2016-03-18

    Applicant: INPHI CORPORATION

    Inventor： Christopher Haywood ,  Chao Xu ,  Fouad G. Tamer

    IPC: G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G11C8/00 ,  H05K7/14 ,  H05K7/20 ,  G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

    Abstract translation: 本发明涉及服务器系统及其方法。 更具体地，本发明的实施例提供了服务器系统内的存储器控​​制器，其中存储器控制器可分离地连接到一个或多个处理器，多个易失性存储器模块和多个固态存储器模块。 该存储器控制器可以连接到其他类似配置的存储器控​​制器。 可以移除和/或更换易失性和固态存储器模块。 还有其它实施例。

    Memory controller system with non-volatile backup storage
    6.
    发明授权
    Memory controller system with non-volatile backup storage 有权
    具有非易失性备份存储的内存控制器系统

    公开(公告)号：US09348705B1

    公开(公告)日：2016-05-24

    申请号：US14316707

    申请日：2014-06-26

    Applicant: INPHI CORPORATION

    Inventor： Shih-Ho Wu ,  Christopher Haywood

    IPC: G06F11/14 ,  G06F12/02

    CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0683 ,  G06F3/0688 ,  G06F11/1441 ,  G06F11/1458 ,  G06F11/1469 ,  G06F11/1662 ,  G06F11/1666 ,  G06F11/2015 ,  G06F12/0246 ,  G06F12/0868 ,  G06F2201/83 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7209 ,  G11C14/0009 ,  Y02D10/13

    Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.

    Abstract translation: 本发明涉及计算机存储系统及其方法。 更具体地，本发明的实施例提供了一种包括非易失性存储器和易失性存储器的隔离存储控制系统。 非易失性存储器包括数据区域和元数据区域。 在电源故障或类似情况下，易失性存储器的内容被复制到非易失性存储器的数据区域，各种系统参数存储在元数据区域。 当系统恢复其操作时，处理元数据区域处的信息，将存储在非易失性存储器的数据区域的内容复制到易失性存储器。 还有其它实施例。

    Memory centric computing
    7.
    发明授权
    Memory centric computing 有权
    以内存为中心的计算

    公开(公告)号：US09348539B1

    公开(公告)日：2016-05-24

    申请号：US14194416

    申请日：2014-02-28

    Applicant: INPHI CORPORATION

    Inventor： Nirmal Raj Saxena ,  David Wang ,  Christopher Haywood ,  Eric McDonald ,  Chao Xu

    IPC: G06F3/06

    CPC classification number: G11C11/005 ,  G11C5/04

    Abstract: A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.

    Abstract translation: 混合存储器系统。 该系统可以包括耦合到耦合到多个DRAM和多个闪存模块的混合存储器缓冲器（HMB）的处理器。 HMB模块可以包括由SerDes（串行器/解串器）接口耦合的存储器存储控制器（MSC）模块和近端存储器处理（NMP）模块。 该系统可以利用混合（混合存储器型）存储器系统架构，其适用于在用于工业标准计算机系统的相同存储器子系统中支持低延迟DRAM设备和低成本NAND闪存器件。

    Systems and methods for error detection and correction in a memory module which includes a memory buffer
    10.
    发明授权
    Systems and methods for error detection and correction in a memory module which includes a memory buffer 有权
    包括存储器缓冲器的存储器模块中用于错误检测和校正的系统和方法

    公开(公告)号：US09015558B2

    公开(公告)日：2015-04-21

    申请号：US14228847

    申请日：2014-03-28

    Applicant: Inphi Corporation

    Inventor： David Wang ,  Christopher Haywood

    IPC: G11C29/00 ,  G06F11/10 ,  G11C7/10 ,  G11C11/408 ,  G11C29/52 ,  H03M13/15 ,  G11C29/04

    CPC classification number: G06F11/1068 ,  G06F11/10 ,  G11C7/1006 ,  G11C11/408 ,  G11C29/52 ,  G11C29/848 ,  G11C2029/0411 ,  H03M13/1515 ,  H03M13/152

    Abstract: The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.

    Abstract translation: 本系统包括存储模块，该存储器模块包含多个RAM芯片，通常为DRAM，以及一个存储器缓冲器，用于缓冲DRAM和主机控制器之间的数据。 存储器缓冲器包括错误检测和校正电路，其布置成确保存储的数据字的完整性。 可以实现这一点的一种方式是通过计算每个数据字的奇偶校验位并将它们与每个数据字并行存储。 如果主机控制器包括自己的错误检测和校正电路，则可以将错误检测和校正电路设置为检测和纠正单个错误或多个错误。 或者，可以确定故障存储单元的位置并将其存储在地址匹配表中，该地址匹配表然后被用于控制将故障单元周围的数据引导到冗余DRAM芯片或在另一实施例中的嵌入式SRAM。

Patent Agency Ranking