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    STACKED DRAM DEVICE AND METHOD OF MANUFACTURE
    301.
    发明申请
    STACKED DRAM DEVICE AND METHOD OF MANUFACTURE 审中-公开

    公开(公告)号：US20190295604A1

    公开(公告)日：2019-09-26

    申请号：US16256887

    申请日：2019-01-24

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang

    IPC: G11C5/06 ,  H01L23/48 ,  H01L25/065 ,  H01L27/108 ,  G11C5/02

    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

    Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices
    302.
    发明申请
    Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices 审中-公开

    公开(公告)号：US20190278722A1

    公开(公告)日：2019-09-12

    申请号：US16243055

    申请日：2019-01-08

    Applicant: Rambus Inc.

    Inventor： John Eric Linstadt

    IPC: G06F13/16 ,  G06F12/06 ,  G11C7/10 ,  G06F12/02 ,  G11C7/22 ,  G11C7/20

    Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
    305.
    发明申请
    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE 审中-公开

    公开(公告)号：US20190266112A1

    公开(公告)日：2019-08-29

    申请号：US16290346

    申请日：2019-03-01

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

    IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

    Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

    DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS
    307.
    发明申请
    DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS 审中-公开

    公开(公告)号：US20190250695A1

    公开(公告)日：2019-08-15

    申请号：US16272346

    申请日：2019-02-11

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE

    IPC: G06F1/3287 ,  G06F1/3293 ,  G06F1/3234 ,  G06F13/16

    CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3293 ,  G06F13/1694 ,  Y02D10/151 ,  Y02D10/157

    Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

    Frequency-agile clock generator
    308.
    发明授权
    Frequency-agile clock generator 有权

    公开(公告)号：US10382023B1

    公开(公告)日：2019-08-13

    申请号：US15969602

    申请日：2018-05-02

    Applicant: Rambus Inc.

    Inventor： Yue Lu ,  Jared L. Zerbe

    IPC: H03K5/00 ,  H03L7/099 ,  H04L7/033 ,  H03L7/24 ,  H03L7/16 ,  H03L7/085 ,  H03L7/083 ,  H03L7/08

    Abstract: A clock generating circuit is operated in a phase-locking mode to generate an output clock signal having a first frequency that is phased-locked with respect to a variable-frequency input clock signal. After a frequency transition in the input clock signal, phase-locking is disabled within the clock generating circuit to transition the output clock signal from the first frequency to a second frequency that lacks phase-alignment with the input clock signal, then a frequency-lock range of the clock generating circuit is adjusted to transition the output clock signal from the second frequency to a third frequency that also lacks phase alignment with the input clock signal. After adjusting the frequency-lock range of the clock generating circuit, phase-locking is re-enabled therein to transition the output clock signal from the third frequency to a fourth frequency that is phase-aligned with the variable-frequency input clock signal.

    Memory system topologies including a buffer device and an integrated circuit memory device
    309.
    发明授权
    Memory system topologies including a buffer device and an integrated circuit memory device 有权

    公开(公告)号：US10381067B2

    公开(公告)日：2019-08-13

    申请号：US15832468

    申请日：2017-12-05

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C7/10 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H01L25/065 ,  H01L25/10 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/22 ,  H01L25/18 ,  H01L23/00

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

    Dual temperature band integrated circuit device
    310.
    发明授权
    Dual temperature band integrated circuit device 有权

    公开(公告)号：US10378967B1

    公开(公告)日：2019-08-13

    申请号：US15794280

    申请日：2017-10-26

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  Frederick A. Ware

    IPC: H03K19/0175 ,  G05F3/24 ,  G01K7/01 ,  G05F1/56

    Abstract: During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.

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