公开(公告)号：US12236999B2

公开(公告)日：2025-02-25

申请号：US17830042

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Paolo Fantini

IPC: G11C11/40 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

Abstract: Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.

公开(公告)号：US20240404606A1

公开(公告)日：2024-12-05

申请号：US18803290

申请日：2024-08-13

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

公开(公告)号：US20240312521A1

公开(公告)日：2024-09-19

申请号：US18593671

申请日：2024-03-01

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Stephen W. Russell ,  Lorenzo Fratin

IPC: G11C16/04 ,  H10B43/10 ,  H10B43/20

CPC classification number: G11C16/0483 ,  H10B43/10 ,  H10B43/20

Abstract: Methods, systems, and devices for trench and multiple pier architecture for three-dimensional memory arrays are described. Manufacturing operations for a memory device may include forming trenches, and subsequently forming multiple types of pier structures extending between the trenches in a first horizontal direction, in a second horizontal direction or both. For example, the trenches may be arranged in a grid-like structure extending in one or more rows and one or more columns. A set of a first type of pier may be formed along each of the trenches, a set of a second type of pier may be formed between adjacent trenches in the first horizontal direction, and a set of a third type of pier may be formed between adjacent trenches in the second horizontal direction.

公开(公告)号：US20240312518A1

公开(公告)日：2024-09-19

申请号：US18586149

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/409 ,  G11C29/50

CPC classification number: G11C11/5642 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/5628 ,  G11C29/50004

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US20240284659A1

公开(公告)日：2024-08-22

申请号：US18440460

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Fabio Pellizzer

IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4094

CPC classification number: H10B12/485 ,  G11C11/4085 ,  G11C11/4094 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

Abstract: Methods, systems, and devices for lateral split digit line memory architectures are described. A memory array may include a first set of word line plates separated from a second set of word line plates by a pillar (e.g., that is configured as a digit line) that interact with the first and second set of word line plates. Further, the memory array may include a set of dielectric piers that are positioned between the pillars, where each dielectric pier contacts a first pillar and a second pillar. Additionally, the memory array may include a set of storage elements and a set of digit lines that are each coupled with a word line plate, a pillar, and a dielectric material that is positioned between each first and second pillar of the pairs of pillars.

公开(公告)号：US20240221829A1

公开(公告)日：2024-07-04

申请号：US18409992

申请日：2024-01-11

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

公开(公告)号：US12026601B2

公开(公告)日：2024-07-02

申请号：US16453528

申请日：2019-06-26

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer

IPC: G06N3/04 ,  G06F17/17 ,  G11C13/00

CPC classification number: G06N3/04 ,  G06F17/17 ,  G11C13/0021 ,  G11C13/0004

Abstract: An apparatus, such as a stacked artificial neural network, can include a semiconductor at a first level. The semiconductor can include first circuitry. A memory can be at a second level. Second circuitry can be at a third level such that the memory is between the first circuitry and the second circuitry. The first circuitry can be configured propagate a first signal to the memory. The memory can be configured to propagate a second signal, based on data stored in the memory, to the second circuitry in response to the first signal. The second circuitry can be configured to generate a data signal based on the second signal.

公开(公告)号：US20240161801A1

公开(公告)日：2024-05-16

申请号：US18409397

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Fabio Pellizzer ,  Enrico Varesi

IPC: G11C8/08 ,  G11C5/06 ,  G11C5/14 ,  G11C8/10 ,  G11C8/14

CPC classification number: G11C8/08 ,  G11C5/06 ,  G11C5/14 ,  G11C8/10 ,  G11C8/14

Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

公开(公告)号：US20240130143A1

公开(公告)日：2024-04-18

申请号：US17968744

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Matteo Impalà ,  Mattia Robustelli ,  Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L45/06 ,  H01L45/143 ,  H01L45/1683

Abstract: A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.

公开(公告)号：US11769551B2

公开(公告)日：2023-09-26

申请号：US17399853

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C13/00 ,  G11C11/402 ,  G11C11/4074 ,  G11C27/00 ,  G11C7/00 ,  H01L45/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: G11C11/5678 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0069 ,  H10N70/24 ,  H10N70/826 ,  H10N70/882 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2013/0052 ,  G11C2013/0092 ,  G11C2213/30 ,  G11C2213/31 ,  G11C2213/71

Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.