公开(公告)号：US20150212945A1

公开(公告)日：2015-07-30

申请号：US14166003

申请日：2014-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Harsh Rawat ,  Gangaikondan Subramani Visweswaran

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract translation: 缓存包括多个高速缓存路径，每个高速缓存路径具有标签存储器字段和对应的数据字段。 通过由读取存储器地址（读取标签部分和读取索引部分）和写入存储器地址（写入标签部分和写入索引部分）定义的同时读取操作，高速缓存确定读取高速缓存命中并从一种高速缓存读取 如读取的存储器地址的读取标签和索引部分所示。 此外，确定写入存储器地址的写入标签和索引部分所指示的写入是否将以与读取相同的一种高速缓存方式进行，以便被冲突。 如果存在这样的冲突，则写入将与读取到一个缓存方式同时实现到与用于读取的不同的缓存方式。

公开(公告)号：US20150198665A1

公开(公告)日：2015-07-16

申请号：US14152879

申请日：2014-01-10

Applicant: STMicroelectronics International N.V.

Inventor： V SRINIVASAN ,  Satinder Singh MALHI ,  Tripti GUPTA

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/318552 ,  G01R31/318594 ,  G01R31/3187

Abstract: A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.

Abstract translation: 一种使用方法测试集成电路的系统和方法，以减少ATPG和LBIST测试期间的电压降。 在一个实施例中，可以将延迟元件添加到用于产生触发各种电子部件的切换的各种时钟信号的时钟电路。 在另一个实施例中，逻辑电路可以被添加到时钟发生电路以隔离时钟域，以便以特定模式启用每个时钟域中的时钟信号。 在又一个实施例中，用于LBIST测试的捕获阶段可以在每个捕获阶段内是不同步的，使得一个LBIST分区的数据捕获可以与其他LBIST分区的其他捕获阶段的时间不同。 最后，另外的实施例ATPG电路也可以被分割，使得逻辑电路一次只能启用一个（或少于所有）ATPG分区。

公开(公告)号：US20150198663A1

公开(公告)日：2015-07-16

申请号：US14152130

申请日：2014-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Danish Hasan Syed

IPC: G01R31/3177 ,  G01R31/3181

CPC classification number: G01R31/31727 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31813

Abstract: A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.

Abstract translation: 半导体芯片包括接收ATPG测试图案并产生响应的时钟脉冲的OCC。 OCC测试电路检测OCC电路的时钟脉冲，并提供调试数据以测试输出可配置逻辑，其也接收来自测试不同DUT触发器的其他电路的结果。 削波测试电路通过向DUT I / O提供脉冲宽度敏感的触发器输出来检测来自OCC的剪辑时钟脉冲的ATPG故障。 IR跌落测试电路检测ATPG故障是否由于某些触发器中的IR降低问题。 脉冲位操作电路改变提供给OCC和OCC产生的时钟脉冲的测试模式。 连接到测试输出可配置逻辑的调试控制器在不同测试结果之间选择供应作为输出测试信号，与ATE上的预期模式数据进行比较，并用于隔离芯片上的错误。

公开(公告)号：US20150168715A1

公开(公告)日：2015-06-18

申请号：US14564237

申请日：2014-12-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Benedetto Vigna ,  Marco Ferrera ,  Sonia Costantini ,  Marco Salina

IPC: G02B26/08 ,  H02N1/00 ,  H04N9/31

CPC classification number: G02B26/0841 ,  B81B3/0045 ,  B81B2201/042 ,  B81B2203/0154 ,  B81C1/00198 ,  G02B27/1006 ,  H02N1/002 ,  H02N1/006 ,  H04N9/3129 ,  H04N9/3135 ,  Y10T29/49002

Abstract: An electrostatically actuated oscillating structure includes a first stator subregion, a second stator subregion, a first rotor subregion and a second rotor subregion. Torsional elastic elements mounted to the first and second rotor subregions define an axis of rotation. A mobile element is coupled to the torsional elastic elements. The stator subregions are electrostatically coupled to respective regions of actuation on the mobile element. The stator subregions exhibit an element of structural asymmetry such that the electrostatic coupling surface between the first stator subregion and the first actuation region differs from the electrostatic coupling surface between the second stator subregion and the second actuation region.

Abstract translation: 静电驱动的振荡结构包括第一定子子区域，第二定子子区域，第一转子子区域和第二转子子区域。 安装到第一和第二转子子区域上的扭转弹性元件限定了旋转轴线。 移动元件联接到扭转弹性元件。 定子子区域静电耦合到移动元件上的各个致动区域。 定子子区域呈现结构不对称的元件，使得第一定子子区域和第一致动区域之间的静电耦合表面与第二定子子区域和第二致动区域之间的静电耦合表面不同。

公开(公告)号：US20150143072A1

公开(公告)日：2015-05-21

申请号：US14526686

申请日：2014-10-29

Applicant: STMicroelectronics International N.V.

Inventor： Herve Sibert ,  Loic Pallardy

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F2212/657

Abstract: A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.

Abstract translation: 内存管理单元（MMU）可以管理地址转换。 MMU可以基于与第一存储器访问请求相关的第一虚拟地址（VA）获得第一中间物理地址（IPA）。 MMU可以基于第一IPA识别第二地址转换表中的第一存储器页条目。 MMU可以在第二高速缓冲存储器中存储基于所识别的第一存储器页条目的第一IPA到PA转换。 MMU可以在第二高速缓冲存储器中存储并且响应于第一存储器页条目的标识，基于第二地址转换中的对应的一个或多个附加存储器页条目的一个或多个附加的IPA到PA转换 表。 一个或多个附加存储器页条目可以与第一存储器页条目相邻。

公开(公告)号：US20150137862A1

公开(公告)日：2015-05-21

申请号：US14086110

申请日：2013-11-21

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil Bahl ,  Shray Khullar

IPC: H03L7/06

CPC classification number: H03L7/06 ,  G01R31/318552 ,  G01R31/318555 ,  G06F1/12

Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.

Abstract translation: 半导体芯片包括能够同步器件上的多个时钟信号的片上时钟控制器（OCC）。 每个OCC控制器接收从一个或多个时钟发生器产生的扫描使能信号和唯一的时钟信号。 接收最慢生成时钟信号的OCC通过内部元稳定寄存器传递，并向处理较快时钟信号的OCC提供外部同步信号。 这些更快时钟的OCC可以使用外部同步信号来同步其时钟并产生测试时钟脉冲。

公开(公告)号：US20150123721A1

公开(公告)日：2015-05-07

申请号：US14072373

申请日：2013-11-05

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha ,  Archit Joshi

IPC: H03K3/84

CPC classification number: H03K3/84

Abstract: In accordance with an embodiment, a method of generating noise includes generating, using a hardware-based noise generator, a plurality of periodic waveforms having different frequencies, weighting, using the hardware-based noise generator, amplitudes of the plurality of periodic waveforms based on a predetermined spectral shape to form a plurality of weighted waveforms, and summing the plurality of plurality of weighted waveforms to form an output random noise signal.

Abstract translation: 根据实施例，一种产生噪声的方法包括：使用基于硬件的噪声发生器生成具有不同频率的多个周期性波形，使用基于硬件的噪声发生器对多个周期波形的幅度进行加权，基于 预定的光谱形状以形成多个加权波形，并且对多个加权波形进行求和以形成输出随机噪声信号。

公开(公告)号：US09025355B2

公开(公告)日：2015-05-05

申请号：US13954908

申请日：2013-07-30

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics PVT Ltd

Inventor： Fabio De Santis ,  Marco Pasotti ,  Abhishek Lal

IPC: G11C5/06 ,  G11C5/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。

公开(公告)号：US09014182B2

公开(公告)日：2015-04-21

申请号：US14101009

申请日：2013-12-09

Applicant: STMicroelectronics International N.V.

Inventor： Gaurav Mathur ,  Pratik Damle

IPC: H04L12/50 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4291 ,  G06F13/38 ,  G06F13/4022

Abstract: A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal.

Abstract translation: 一种电路，包括：设备确定器，被配置为在第一操作模式中，经由至少一个控制线和至少一个信号线中的至少一个接收设备选择信号; 以及设备路由器，被配置为在第二操作模式中，在至少一个控制线路与至少一个信号线路之间的至少一个和至少一个取决于所述设备选择信号的设备之间路由信号。

公开(公告)号：US09013212B2

公开(公告)日：2015-04-21

申请号：US13931343

申请日：2013-06-28

Applicant: STMicroelectronics International N.V.

Inventor： Vinod Kumar

IPC: H03B1/00 ,  G11C7/10 ,  H03K3/02

CPC classification number: H03K3/02 ,  G11C7/1057 ,  G11C7/1069

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract translation: 输出驱动器电路包括具有公共电流路径的第一，第二，第三和第四晶体管，其中第一晶体管的栅极接收第一开关信号，第二晶体管的栅极接收第一参考电压，第三晶体管的栅极 晶体管接收第二参考电压，并且第四晶体管的栅极接收第二开关信号，并且其中第一电容器耦合在第一晶体管的栅极和第三晶体管的栅极之间，第二电容器耦合在栅极之间 的第二晶体管和第四晶体管的栅极，并且在耦合第二和第三晶体管的节点处提供输出信号。