公开(公告)号：US20080121863A1

公开(公告)日：2008-05-29

申请号：US11753528

申请日：2007-05-24

Applicant: Wei-Su CHEN

Inventor： Wei-Su CHEN

IPC: H01L45/00

CPC classification number: G11C13/0004 ,  H01L27/2409 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

Abstract: A phase change memory device is provided. The phase change memory device includes a substrate comprising a stacked structure. The stacked structure comprises a plurality of insulating layers and conductive layers. Any two of the conductive layers are spaced apart by one of the conductive layers. A first electrode structure with a first sidewall and a second sidewall is formed on the stacked structure. A plurality of heating electrodes is placed on the conductive layers and adjacent to the first sidewall and the second sidewall of the first electrode structure. A pair of phase change material spacers is placed on the first sidewall and the second sidewall of the first electrode structure. The phase change material sidewalls cover the plurality of heating electrodes.

Abstract translation: 提供了相变存储器件。 相变存储器件包括包括堆叠结构的衬底。 堆叠结构包括多个绝缘层和导电层。 导电层中的任何两个由一个导电层隔开。 具有第一侧壁和第二侧壁的第一电极结构形成在堆叠结构上。 多个加热电极放置在导电层上并与第一电极结构的第一侧壁和第二侧壁相邻。 一对相变材料间隔物被放置在第一电极结构的第一侧壁和第二侧壁上。 相变材料侧壁覆盖多个加热电极。

公开(公告)号：US20080099144A1

公开(公告)日：2008-05-01

申请号：US12003342

申请日：2007-12-21

Applicant: Hong Change ,  Hung Lu

Inventor： Hong Change ,  Hung Lu

IPC: H01L21/306

CPC classification number: H01L21/67086 ,  H01L21/31111

Abstract: The present etching system includes a processing tank with an etching solution containing silicon, a cooling tank, a pre-heating tank, a first pipe for transferring the etching solution from the processing tank to the cooling tank, a second pipe for transferring the etching solution from the cooling tank to the pre-heating tank, and a third pipe for transferring the etching solution from the pre-heating tank to the processing tank. The present method for treating the etching solution first performs an etching process using the etching solution, which is then cooled to a first temperature to form a silicon-saturated etching solution. After silicon-containing particles larger than a predetermined size are filtered out, the silicon-saturated etching solution is heated to a second temperature to form a non-saturated etching solution for performing another etching process later. The second temperature is preferably at least 10° C. higher than the first temperature.

Abstract translation: 本蚀刻系统包括具有含硅蚀刻液的处理槽，冷却槽，预热槽，将蚀刻液从处理槽输送到冷却槽的第一管，用于将蚀刻液 从冷却槽到预热槽，以及用于将蚀刻液从预热槽输送到处理槽的第三管。 本蚀刻溶液的处理方法首先使用蚀刻液进行蚀刻处理，然后冷却至第一温度，形成硅饱和蚀刻液。 在大于预定尺寸的含硅颗粒被滤出之后，将硅饱和蚀刻溶液加热到第二温度以形成用于稍后进行另一蚀刻处理的非饱和蚀刻溶液。 第二温度优选比第一温度高至少10℃。

公开(公告)号：US20080076241A1

公开(公告)日：2008-03-27

申请号：US11641131

申请日：2006-12-19

Applicant: Tsung-Hsun Yang ,  Hsiao-Che Wu ,  Feng-Chun Chen ,  Chien-Hsun Pan

Inventor： Tsung-Hsun Yang ,  Hsiao-Che Wu ,  Feng-Chun Chen ,  Chien-Hsun Pan

IPC: H01L21/3205

CPC classification number: H01L21/32139 ,  H01L21/3211

Abstract: A method for reducing stress between a conductive layer and a mask layer is provided. The method for reducing stress comprises a step of performing a plasma treatment with a nitrogen-containing gas to modify a surface of the conductive layer prior to the formation of the mask layer upon the surface. The method is useful for the manufacture of a gate, and the method for manufacturing the gate comprises the steps of providing a substrate; and sequentially depositing an oxide layer, a conductive layer, and a mask layer on the substrate to form a gate stack structure. The conductive layer is subjected to a surface plasma treatment with a nitrogen-containing gas prior to depositing the mask layer to modify its surface.

Abstract translation: 提供了一种用于减小导电层和掩模层之间的应力的方法。 减少应力的方法包括在表面形成掩模层之前，用含氮气体进行等离子体处理以改变导电层的表面的步骤。 该方法对于制造栅极是有用的，并且用于制造栅极的方法包括以下步骤：提供基板; 并在衬底上依次沉积氧化物层，导电层和掩模层以形成栅叠层结构。 在沉积掩模层以改变其表面之前，用含氮气体对导电层进行表面等离子体处理。

公开(公告)号：US07336340B2

公开(公告)日：2008-02-26

申请号：US10777417

申请日：2004-02-11

Applicant: Peter Wang

Inventor： Peter Wang

IPC: G03B27/68 ,  G03B27/52 ,  G03B27/32

CPC classification number: G03F7/70533 ,  G03F7/70558

Abstract: A method of adjusting exposure error for multiple products is described. First, one Photo Feed Back System (PFBS) suited to host-product or miscellaneous product is chosen. Different standard points and compensation difference for host-product or miscellaneous product are provided. Then, the PFBS parameter is calculated as an exposure adjustment value. The standard point and compensation difference for miscellaneous product are dependent on host-product.

Abstract translation: 描述了一种调整多个产品的曝光误差的方法。 首先，选择适合主机产品或其他产品的一个照片反馈系统（PFBS）。 提供主机产品或杂项产品的不同标准点和补偿差异。 然后，将PFBS参数计算为曝光调整值。 杂项产品的标准点和补偿差异取决于主机产品。

公开(公告)号：US20080035961A1

公开(公告)日：2008-02-14

申请号：US11552492

申请日：2006-10-24

Applicant: Yi-Chan Chen ,  Wen-Han Wang

Inventor： Yi-Chan Chen ,  Wen-Han Wang

IPC: H01L27/148

CPC classification number: H01L45/124 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.

Abstract translation: 相变存储器包括形成在基板上的底部电极。 在底部电极上形成第一隔离层。 顶部电极形成在隔离层上。 第一相变材料形成在第一隔离层中，其中顶部电极和底部电极经由第一相变材料电连接。 由于相变材料的直径可以小于光刻工艺的分辨率极限，所以可以减小相变材料图案的状态转换的工作电流，从而降低相变存储器的功耗 设备。

公开(公告)号：US20080032471A1

公开(公告)日：2008-02-07

申请号：US11580807

申请日：2006-10-13

Applicant: Wen-Shuo Kuo ,  Chao-Hsi Chung ,  Yung Yao Lee ,  Hui-Min Li

Inventor： Wen-Shuo Kuo ,  Chao-Hsi Chung ,  Yung Yao Lee ,  Hui-Min Li

IPC: H01L21/8242

CPC classification number: H01L21/76224 ,  H01L27/1087

Abstract: A method for manufacturing a shallow trench isolation structure in a deep trench and application thereof are provided, wherein the deep trench having an upper electrode and an insulation layer on the upper electrode is formed in a substrate which has a pad insulation layer. The method comprises the following steps: forming a hard mask on the first insulation layer, doping a first portion of the hard mask, removing the undoped portion of the hard mask to expose a portion of the first insulation layer and reserve the first portion of the hard mask, removing the exposed portion of the first insulation layer to expose a portion of the upper electrode, and forming a conductive layer on the exposed portion of the upper electrode wherein a predetermined distance exists between the upper surface of the conductive layer and the pad insulation layer.

Abstract translation: 提供一种在深沟槽中制造浅沟槽隔离结构的方法及其应用，其中在具有衬垫绝缘层的衬底中形成具有上电极和上电极上的绝缘层的深沟槽。 该方法包括以下步骤：在第一绝缘层上形成硬掩模，掺杂硬掩模的第一部分，去除硬掩模的未掺杂部分以暴露第一绝缘层的一部分并保留第一绝缘层的第一部分 去除所述第一绝缘层的暴露部分以暴露所述上电极的一部分，以及在所述上电极的暴露部分上形成导电层，其中在所述导电层的所述上表面和所述焊盘之间存在预定距离 绝缘层。

公开(公告)号：US07326992B2

公开(公告)日：2008-02-05

申请号：US11468202

申请日：2006-08-29

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在具有多个浮动栅极（160）的存储单元（110）中，在浮置栅极之前形成选择栅极（140）。 在一些实施例中，存储器单元还具有在选择栅极之后形成的控制栅极（170）。 衬底隔离区（220）形成在半导体衬底（120）中。 衬底隔离区突出于衬底上方。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区露出。 在浮动栅极层上形成电介质（164），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些控制栅极和浮置栅极独立于光刻对准来定义。 在另一方面，非易失性存储单元具有至少两个导电浮动栅极（160）。 覆盖浮动栅极的介电层（164）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的侧壁的连续特征。 每个控制栅极（160）覆盖在电介质层的连续特征上并且也覆盖在浮动栅极上。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US20070295949A1

公开(公告)日：2007-12-27

申请号：US11615909

申请日：2006-12-22

Applicant: Chien-Min Lee

Inventor： Chien-Min Lee

IPC: H01L47/00

CPC classification number: H01L45/1675 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.

Abstract translation: 一种相变存储器件，包括电极，在其交叉区域交叉并接触电极的相变层和包括源极和漏极的晶体管，其中晶体管的漏极电连接电极或相变层是 披露

公开(公告)号：US20070291533A1

公开(公告)日：2007-12-20

申请号：US11758559

申请日：2007-06-05

Applicant: Yen Chuo ,  Wen-Han Wang ,  Min-Hung Lee ,  Hong-Hui Hsu ,  Chien-Min Lee ,  Te-Sheng Chao ,  Yi-Chan Chen ,  Wei-Su Chen

Inventor： Yen Chuo ,  Wen-Han Wang ,  Min-Hung Lee ,  Hong-Hui Hsu ,  Chien-Min Lee ,  Te-Sheng Chao ,  Yi-Chan Chen ,  Wei-Su Chen

IPC: G11C11/00

CPC classification number: H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

Abstract: The invention provides a phase change memory device comprising a stacked structure disposed on a substrate. The stacked structure comprises a first electrode, a second electrode overlying the first electrode and an insulating layer interposed between the first and the second electrodes. A memory spacer is formed on part of the sidewall of the stacked structure to contact the first electrode, the insulating layer and the second electrode.

Abstract translation: 本发明提供一种相变存储器件，其包括设置在衬底上的层叠结构。 层叠结构包括第一电极，覆盖第一电极的第二电极和插在第一和第二电极之间的绝缘层。 在层叠结构的侧壁的一部分上形成有与第一电极，绝缘层和第二电极接触的记忆间隔物。

公开(公告)号：US20070267691A1

公开(公告)日：2007-11-22

申请号：US11459360

申请日：2006-07-23

Applicant: Yu-Chi Chen ,  Jih-Wen Chou ,  Frank Chen

Inventor： Yu-Chi Chen ,  Jih-Wen Chou ,  Frank Chen

IPC: H01L29/94

CPC classification number: H01L29/66628 ,  H01L21/28061 ,  H01L29/66621 ,  H01L29/7834

Abstract: A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the pad material layer. A gate dielectric layer is formed on the surface of the substrate in the trench. A stacked gate structure is formed in the trench, wherein the top surface of a conductive layer of the stacked gate structure is higher than the surface of the pad material layer. A spacer material layer is formed conformably on the substrate. Portions of the spacer material layer and the pad material layer are removed so as to form a pair of first spacers and a pair of pad blocks. A source/drain is formed on the substrate beside the stacked gate structure.

Abstract translation: 提供了金属氧化物半导体晶体管的制造方法。 提供基板。 源极/漏极延伸区域形成在衬底中。 在基板上形成具有低介电常数的焊盘材料层。 在衬底和衬垫材料层中形成沟槽。 栅极电介质层形成在沟槽中的衬底的表面上。 在沟槽中形成堆叠的栅极结构，其中层叠栅极结构的导电层的顶表面高于焊盘材料层的表面。 衬垫材料层在衬底上顺应地形成。 去除间隔材料层和垫材料层的一部分，以形成一对第一间隔物和一对垫块。 源极/漏极形成在堆叠栅极结构旁边的衬底上。