公开(公告)号：US20190385320A1

公开(公告)日：2019-12-19

申请号：US16548138

申请日：2019-08-22

Applicant: STMicroelectronics SA

Inventor： Manu Alibay ,  Olivier Pothier ,  Victor Macela ,  Alain Bellon ,  Arnaud Bourge

IPC: G06T7/521 ,  G01S17/08

Abstract: The method of determination of a depth map of a scene comprises generation of a distance map of the scene obtained by time of flight measurements, acquisition of two images of the scene from two different viewpoints, and stereoscopic processing of the two images taking into account the distance map. The generation of the distance map includes generation of distance histograms acquisition zone by acquisition zone of the scene, and the stereoscopic processing includes, for each region of the depth map corresponding to an acquisition zone, elementary processing taking into account the corresponding histogram.

公开(公告)号：US10480833B2

公开(公告)日：2019-11-19

申请号：US15801505

申请日：2017-11-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Rafael Augusto Prieto Herrera ,  Jean-Philippe Colonna ,  Perceval Coudrain

IPC: F25B15/00 ,  F28F3/00 ,  H05K7/20 ,  G06F1/20 ,  H01L23/498 ,  H01L23/427 ,  H01L23/433

Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.

公开(公告)号：US10476383B2

公开(公告)日：2019-11-12

申请号：US16012410

申请日：2018-06-19

Applicant: STMicroelectronics SA

Inventor： Thierry Di Gilio

IPC: H02M3/07 ,  H02M1/36 ,  H03K17/30 ,  H02M1/14 ,  H02M1/00

Abstract: The disclosure relates to a negative charge pump circuit including a first capacitor; a first selector switch; a second selector switch; and a control circuit designed to, in a first phase of operation, alternately control the first and second selector switches in a first configuration in which the first and second electrodes of the first capacitor are respectively linked to the first and second nodes and in a second configuration in which the first and second electrodes of the first capacitor are respectively linked to the second and third nodes. In a second phase of operation, the control circuit forces the first selector switch to link the first electrode of the first capacitor to the second node and control the second selector switch so as to alternately link the second electrode of the first capacitor to the second and to the third node.

公开(公告)号：US20190319454A1

公开(公告)日：2019-10-17

申请号：US15952466

申请日：2018-04-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Radhakrishnan SITHANANDAM ,  Divya AGARWAL ,  Jean JIMENEZ ,  Malathi KAR

IPC: H02H9/04 ,  H01L27/02 ,  H01L27/07

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.

公开(公告)号：US10432154B2

公开(公告)日：2019-10-01

申请号：US15609639

申请日：2017-05-31

Applicant: STMicroelectronics SA

Inventor： Lionel Vogt

IPC: H03G3/10 ,  H03F3/42 ,  H03F1/02 ,  H03F1/30 ,  H03F3/189 ,  H03F3/193 ,  H03G3/30

Abstract: A radiofrequency (RF) amplifier includes an input terminal, an output terminal, and a power supply and biasing stage having an output coupled to the input terminal. An amplification stage of the RF amplifier includes a first transistor having a control terminal coupled to the input terminal and a first conduction terminal coupled to the output terminal. The power supply and biasing stage is configured to generate a bias voltage at the control terminal of the first transistor to simultaneously regulate a power supply voltage of the amplification stage to a first voltage and a bias current of the amplification stage to a first current.

公开(公告)号：US20190285694A1

公开(公告)日：2019-09-19

申请号：US16424034

申请日：2019-05-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent HUARD ,  Chittoor PARTHASARATHY

IPC: G01R31/28

Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.

公开(公告)号：US10395013B2

公开(公告)日：2019-08-27

申请号：US15390850

申请日：2016-12-27

Applicant: STMicroelectronics SA

Inventor： Jocelyn Leheup ,  Herve Sibert

IPC: G06F21/00 ,  G06F21/16 ,  G06F21/57 ,  G06F21/44 ,  G06F21/84 ,  H04N21/4363 ,  H04N21/4367 ,  H04L29/06 ,  G06F21/10

Abstract: A signal is protected against an attack by an enhancement process that checks the conformity of an actual state of the signal with respect to an expected state. A protective action is exercised on the signal if the actual state of the signal is not in conformity with the expected state, so as to neutralize or nullify said attack.

公开(公告)号：US10236865B2

公开(公告)日：2019-03-19

申请号：US15952804

申请日：2018-04-13

Applicant: STMicroelectronics SA

Inventor： Bruno Grelaud ,  Sebastien Pruvost

IPC: H04B1/18 ,  H04B3/26 ,  H03H11/28 ,  H03H11/32 ,  H03H11/24 ,  H01Q1/50 ,  H04L25/12 ,  H04B1/04 ,  H04L25/02 ,  H03H7/25 ,  H03H7/40 ,  H03H11/30

Abstract: An attenuator having an impedance that is controllable by a first setpoint signal is coupled to a transmission line. A matching circuit having an impedance that is controllable by a second setpoint signal is also coupled to the transmission line. A transformer circuit block also coupled to the transmission line has a complex impedance. A control circuit sets the first and second setpoint signals so as to control a conjugate impedance relationship between the variable impedances presented by the attenuator and matching circuit relative to the complex impedance of the transformer circuit.

公开(公告)号：US20180302063A1

公开(公告)日：2018-10-18

申请号：US15952804

申请日：2018-04-13

Applicant: STMicroelectronics SA

Inventor： Bruno GRELAUD ,  Sebastien PRUVOST

IPC: H03H11/28 ,  H03H11/32 ,  H03H11/24 ,  H01Q1/50 ,  H04L25/02 ,  H04L25/12 ,  H04B3/26 ,  H04B1/04 ,  H04B1/18

CPC classification number: H03H11/28 ,  H01Q1/50 ,  H03H7/25 ,  H03H7/40 ,  H03H11/245 ,  H03H11/30 ,  H03H11/32 ,  H04B1/0458 ,  H04B1/18 ,  H04B3/26 ,  H04L25/0278 ,  H04L25/12

Abstract: An attenuator having an impedance that is controllable by a first setpoint signal is coupled to a transmission line. A matching circuit having an impedance that is controllable by a second setpoint signal is also coupled to the transmission line. A transformer circuit block also coupled to the transmission line has a complex impedance. A control circuit sets the first and second setpoint signals so as to control a conjugate impedance relationship between the variable impedances presented by the attenuator and matching circuit relative to the complex impedance of the transformer circuit.

公开(公告)号：US20180278021A1

公开(公告)日：2018-09-27

申请号：US15992573

申请日：2018-05-30

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/12 ,  H01S5/10 ,  H01S5/026 ,  H01S5/02 ,  H01S5/343 ,  H01S5/022 ,  G02B6/12 ,  G02B6/34 ,  G02B6/30 ,  H01S5/187 ,  H01S5/323 ,  H01S5/042

CPC classification number: H01S5/1237 ,  G02B6/30 ,  G02B6/34 ,  G02B2006/12061 ,  G02B2006/12121 ,  H01L2224/32 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/0421 ,  H01S5/1014 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/187 ,  H01S5/323 ,  H01S5/343 ,  H01S2301/166

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).