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    Image sensing device
    32.
    发明授权
    Image sensing device 有权

    公开(公告)号：US12113085B2

    公开(公告)日：2024-10-08

    申请号：US17559304

    申请日：2021-12-22

    申请人： SK hynix Inc.

    发明人： Jae Hyung Jang

    IPC分类号： H01L27/146

    CPC分类号： H01L27/1463

    摘要： An image sensing device includes a plurality of unit pixels, each of which includes a plurality of sub-pixels. Each of the unit pixels is structured to respond to incident light to produce photocharges indicative of detected incident light and includes sub-pixels. Each sub-pixel includes a control region configured to generate, within a substrate in which the sub-pixels are disposed, a current that carries the photocharges, a detection region spaced from the control region and configured to capture the photocharges carried by the current, a plurality of first isolation portions disposed between two adjacent sub-pixels, a second isolation portion disposed to surround the sub-pixels, and a voltage applying region disposed at a center portion of the unit pixel and configured to receive a first voltage.

    Out-of-order bit-flipping decoders for non-volatile memory devices
    34.
    发明授权
    Out-of-order bit-flipping decoders for non-volatile memory devices 有权

    公开(公告)号：US12112041B2

    公开(公告)日：2024-10-08

    申请号：US17950528

    申请日：2022-09-22

    申请人： SK hynix Inc.

    发明人： Fan Zhang ,  Meysam Asadi ,  Haobo Wang

    IPC分类号： G06F3/06 ,  H03M13/11

    CPC分类号： G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1128

    摘要： Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    35.
    发明公开
    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240334706A1

    公开(公告)日：2024-10-03

    申请号：US18471165

    申请日：2023-09-20

    申请人： SK hynix Inc.

    发明人： Ki Deok KIM

    IPC分类号： H10B43/40 ,  H10B41/41

    CPC分类号： H10B43/40 ,  H10B41/41 ,  G11C16/08

    摘要： A memory device, and a method of manufacturing the same, includes a well formed in a substrate. The memory device also includes an insulating liner layer formed between the well and the substrate, the insulating linear layer enclosing the well. The memory device further includes first, second, and third junction regions included in the well enclosed by the insulating liner layer, the first, second, and third junction regions being spaced apart from each other. The memory device additionally includes a gate pattern disposed on the well between the first and second junction regions and a blocking layer included in the well, the blocking layer disposed between the second and third junction regions.

    IMAGE SENSING DEVICE
    36.
    发明公开
    IMAGE SENSING DEVICE 审中-公开

    公开(公告)号：US20240332331A1

    公开(公告)日：2024-10-03

    申请号：US18508570

    申请日：2023-11-14

    申请人： SK hynix Inc.

    发明人： Ho Young KWAK

    IPC分类号： H01L27/146 ,  H01L23/538

    CPC分类号： H01L27/1463 ,  H01L23/5384

    摘要： Image sensing devices are disclosed. In an embodiment, an image sensing device includes a semiconductor substrate including a first surface and a second surface facing or opposite to the first surface, and structured to include a pixel region in which photoelectric conversion elements are formed to correspond to unit pixels and a pad region that is located outside the pixel region while having an electrode pad, a pixel isolation pattern disposed between the photoelectric conversion elements in the semiconductor substrate, and a pad isolation pattern disposed between the pixel region and the pad region in the semiconductor substrate.

    SEMICONDUCTOR DEVICES
    39.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240331752A1

    公开(公告)日：2024-10-03

    申请号：US18737111

    申请日：2024-06-07

    申请人： SK hynix Inc.

    发明人： Ki Hun KWON ,  Jae Il KIM

    IPC分类号： G11C7/22 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12

    CPC分类号： G11C7/222 ,  G11C7/109 ,  G11C5/063 ,  G11C8/12

    摘要： A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.

    LOW-POWER MEMORY SYSTEM AND MEMORY CONTROLLER WITH COMPATIBILITY AND AN OPERATION METHOD THEREOF
    40.
    发明公开
    LOW-POWER MEMORY SYSTEM AND MEMORY CONTROLLER WITH COMPATIBILITY AND AN OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20240331744A1

    公开(公告)日：2024-10-03

    申请号：US18461504

    申请日：2023-09-06

    申请人： SK hynix Inc.

    发明人： Myung Jin JO

    IPC分类号： G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/1069 ,  G11C7/1063 ,  G11C7/222

    摘要： A memory system includes at least one memory chip including first information regarding internal configurations and operational characteristics, and a memory controller configured to perform a data input/output operation on the at least one memory chip. The memory controller includes a core-processor engaged with firmware configured to generate at least one first command for controlling an operation associated with the first information, a memory control sequence generator configured to generate at least one second command for controlling an operation performed on a memory chip which includes second information, and a core interface configured to, when the first information is included in the second information, handover, to the core-processor from the memory control sequence generator, a process for generating some of the at least one command associated with a part of the first information, the part not included in the second information.