公开(公告)号：US20240304657A1

公开(公告)日：2024-09-12

申请号：US18128218

申请日：2023-03-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yi-Chun Teng ,  Ming-Che Tsai ,  Ping-Chia Shih ,  Yi-Chang Huang ,  Wen-Lin Wang ,  Yu-Fan Hu ,  Ssu-Yin Liu ,  Yu-Nong Chen ,  Pei-Tsen Shiu ,  Cheng-Tzung Tsai

IPC分类号： H01L27/06

CPC分类号： H01L28/24 ,  H01L27/0629

摘要： A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

公开(公告)号：US12087635B2

公开(公告)日：2024-09-10

申请号：US18335154

申请日：2023-06-15

申请人： United Microelectronics Corp.

发明人： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823425 ,  H01L21/823437 ,  H01L21/8249 ,  H01L27/0251 ,  H01L29/0607 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/7832 ,  H01L29/7835 ,  H01L29/78

摘要： A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US12080622B2

公开(公告)日：2024-09-03

申请号：US18136329

申请日：2023-04-18

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

摘要： A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US20240290771A1

公开(公告)日：2024-08-29

申请号：US18657811

申请日：2024-05-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC分类号： H01L27/02

CPC分类号： H01L27/0207

摘要： An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3≤D3−S, L4≤D4−S, and D3≠D4.

公开(公告)号：US20240284651A1

公开(公告)日：2024-08-22

申请号：US18123992

申请日：2023-03-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Chen Sun

IPC分类号： H10B10/00

CPC分类号： H10B10/12

摘要： A method for fabricating a static random access memory (SRAM) includes the steps of forming a first fin-shaped structure for a first pull-down (PD) transistor on a substrate, forming a second fin-shaped structure for a second PD transistor on the substrate, forming a third fin-shaped structure for a first pass gate (PG) transistor on the substrate, and forming a fourth fin-shaped structure for a second PG transistor on the substrate. Preferably, the first fin-shaped structure and the second fin-shaped structure include a first recess therebetween and the third fin-shaped structure and the fourth fin-shaped structure include no recess therebetween.

公开(公告)号：US12063871B2

公开(公告)日：2024-08-13

申请号：US18230189

申请日：2023-08-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chiu-Jung Chiu ,  Ya-Sheng Feng ,  I-Ming Tseng ,  Yi-An Shih ,  Yu-Chun Chen ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC分类号： H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC分类号： H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

摘要： A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

公开(公告)号：US20240266435A1

公开(公告)日：2024-08-08

申请号：US18120980

申请日：2023-03-13

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ming-Hua Tsai ,  Chin-Chia Kuo ,  Wei-Hsuan Chang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/6659

摘要： A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.

公开(公告)号：US20240266393A1

公开(公告)日：2024-08-08

申请号：US18119797

申请日：2023-03-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： CHUNYUAN QI ,  XINGXING CHEN ,  ZHUONA MA ,  HUI LIU

IPC分类号： H01L29/06 ,  H01L21/308 ,  H01L27/12 ,  H01L29/16

CPC分类号： H01L29/0657 ,  H01L21/3086 ,  H01L27/1203 ,  H01L29/1604

摘要： A metasurface structure includes a substrate having a first region and a second region not overlapping with the first region; a first pillar element within the first region on the substrate; and a second pillar element within the second region on the substrate. The first pillar element has a first sectional profile and the second pillar element has a second sectional profile that is different from the first sectional profile. At least one of the first sectional profile and the second sectional profile is of a non-rectangular shape.

公开(公告)号：US12057483B2

公开(公告)日：2024-08-06

申请号：US18078057

申请日：2022-12-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/42368 ,  H01L29/0607 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US12057401B2

公开(公告)日：2024-08-06

申请号：US18226784

申请日：2023-07-27

申请人： UNITED MICROELECTRONICS CORP.

发明人： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC分类号： H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

摘要： A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.