公开(公告)号：US20160105194A1

公开(公告)日：2016-04-14

申请号：US14511613

申请日：2014-10-10

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： MAHESH MADHAVAN KUMBARANTHODIYIL ,  Sandeep Monangi

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/122 ,  H03M1/466

Abstract: In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.

Abstract translation: 在示例实施例中，提供了一种促进被动模拟采样和保持的模数转换器（ADC），并且包括一对二进制加权转换电容器阵列，一对采样电容器和配置每个转换电容器阵列的多个开关 用于采样相位的采样电容器，电荷转移阶段和位试验阶段。 在采样阶段，采样电容器与转换电容器分离并耦合到模拟输入电压。 在电荷转移阶段期间，采样电容器耦合到转换电容器并与模拟输入电压分离。 在位试验阶段，采样电容器与转换电容器分离。

公开(公告)号：US20160099692A1

公开(公告)日：2016-04-07

申请号：US14504540

申请日：2014-10-02

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： VINAYAK MUKUND KULKARNI

IPC: H03F3/16

CPC classification number: H03F3/45183 ,  H03F2203/45248 ,  H03F2203/45626 ,  H03F2203/45644 ,  H03F2203/45646

Abstract: In an example embodiment, an amplifier having high gain and high slew rate is provided and includes a pair of input transistors to which input voltage is applied, a pair of diode-connected loads coupled to the input transistors, at least one pair of current sources coupled to the diode-connected loads, and a bias control configured to turn off the at least one pair of current sources to enable high slew rate for the amplifier and to turn on the at least one pair of current sources to enable high gain for the amplifier. In specific embodiments, the current sources include transistors, the bias control controls a bias voltage to the current sources, and the bias voltage is driven to the supply voltage (VDD) to turn off the current sources.

Abstract translation: 在示例实施例中，提供了具有高增益和高转换速率的放大器，并且包括一对输入电压施加到的输入晶体管，耦合到输入晶体管的一对二极管连接的负载，至少一对电流源 耦合到所述二极管连接的负载，以及偏置控制，被配置为关断所述至少一对电流源，以使所述放大器能够实现高转换速率，并且接通所述至少一对电流源，以使所述至少一对电流源能够获得高增益 放大器 在具体实施例中，电流源包括晶体管，偏置控制控制到电流源的偏置电压，偏置电压被驱动到电源电压（VDD）以截止电流源。

公开(公告)号：US09298988B2

公开(公告)日：2016-03-29

申请号：US14076030

申请日：2013-11-08

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Prasanna Baja Thirumaleshwara ,  Vijaykumar Nagarajan

IPC: G06K9/00 ,  G06K9/46 ,  G06K9/62 ,  G06T11/60

CPC classification number: G06K9/00624 ,  G06K9/4604 ,  G06K9/4642 ,  G06K9/6267 ,  G06K9/6269 ,  G06N99/005 ,  G06T11/60

Abstract: An exemplary object detection method includes generating feature block components representing an image frame, and analyzing the image frame using the feature block components. For each feature block row of the image frame, feature block components associated with the feature block row are evaluated to determine a partial vector dot product for detector windows that overlap a portion of the image frame including the feature block row, such that each detector window has an associated group of partial vector dot products. The method can include determining a vector dot product associated with each detector window based on the associated group of partial vector dot products, and classifying an image frame portion corresponding with each detector window as an object or non-object based on the vector dot product. Each feature block component can be moved from external memory to internal memory once implementing the exemplary object detection method.

Abstract translation: 示例性对象检测方法包括生成表示图像帧的特征块分量，以及使用特征块分量来分析图像帧。 对于图像帧的每个特征块行，评估与特征块行相关联的特征块分量，以确定与包括特征块行的图像帧的一部分重叠的检测器窗口的部分矢量点积，使得每个检测器窗口 具有相关组的部分矢量点积。 该方法可以包括基于相关组的部分矢量点积来确定与每个检测器窗口相关联的矢量点积，并且基于矢量点积将对应于每个检测器窗口的图像帧部分分类为对象或非对象。 一旦实现了示例性对象检测方法，每个特征块组件可以从外部存储器移动到内部存储器。

公开(公告)号：US20160072275A1

公开(公告)日：2016-03-10

申请号：US14477236

申请日：2014-09-04

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： TREVOR CLIFFORD CALDWELL ,  COREY PETERSEN ,  DAVID NELSON ALLDRED ,  HAJIME SHIBATA

IPC: H02H7/12 ,  H03M3/00

CPC classification number: H02H7/12 ,  H03M3/30 ,  H03M3/36 ,  H03M3/464 ,  H03M3/484

Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.

Abstract translation: Δ-Σ调制器不能很好地处理过载，如果输入超出调制器的满量程范围，通常会变得不稳定。 为了提供过载保护，改进的技术将过载检测器嵌入到Δ-Σ调制器中。 当检测到过载条件时，调节ΔΣ调制器的系数以适应过载输入。 改进的技术有利地允许Δ-Σ调制器在没有复位的情况下优雅地处理过载，并且以降低的分辨率提供更大的动态范围。 此外，可以以这样的方式调整Δ-Σ调制器的系数，以确保噪声传递函数不受影响。

公开(公告)号：US20150357982A1

公开(公告)日：2015-12-10

申请号：US14296247

申请日：2014-06-04

Applicant: Analog Devices Technology

Inventor： EBERHARD BRUNNER

IPC: H03G1/00 ,  H03F3/04

CPC classification number: H03G1/0017 ,  H03F3/04 ,  H03F3/45 ,  H03F3/45085 ,  H03F2203/45274 ,  H03F2203/45392 ,  H03F2203/45601 ,  H03F2203/45612 ,  H03G1/0023

Abstract: A transconductance gain stage including a pair of gain transistors, each gain transistor having a base and an emitter, the emitter of each gain transistor electrically coupled to a degenerating resistor, and the emitter of each gain transistor connected to a gain resistor.

Abstract translation: 跨导增益级包括一对增益晶体管，每个增益晶体管具有基极和发射极，每个增益晶体管的发射极电耦合到退化电阻器，并且每个增益晶体管的发射极连接到增益电阻器。

公开(公告)号：US09203426B2

公开(公告)日：2015-12-01

申请号：US14302173

申请日：2014-06-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Jialin Zhao ,  Richard E. Schreier ,  Jose Barreiro Silva ,  Hajime Shibata ,  Wenhua W. Yang ,  Yunzhi Dong

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M3/378 ,  H03M1/1019 ,  H03M1/1038 ,  H03M1/74 ,  H03M3/37 ,  H03M3/384 ,  H03M3/388 ,  H03M3/464

Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).

Abstract translation: 数模转换器（DAC）广泛应用于电子产品。 DAC通常不理想，并且通常表现出错误，例如静态失配错误。 本公开描述了用于连续时间Δ-Σ调制器（CTDSM）中的DAC静态失配的数字校准技术。 该方法利用DAC单元元件（UE）本身来测量彼此的不匹配。 没有额外的电路，除了DAC驱动器或比较器中的逻辑设计。 该方法是高性能CTDSM的有吸引力的校准技术，特别是对于具有低过采样率（OSR）的多千兆赫兹范围内的高速系统。

公开(公告)号：US09203350B2

公开(公告)日：2015-12-01

申请号：US14185701

申请日：2014-02-20

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dennis A. Dempsey ,  Sean Brennan ,  Colin Lyden ,  John Jude O'Donnell

IPC: H03F1/22 ,  H03F3/45 ,  H03M1/76 ,  H03M1/80

CPC classification number: H03F1/223 ,  H03F3/45475 ,  H03F2200/156 ,  H03F2203/45116 ,  H03F2203/45528 ,  H03F2203/45536 ,  H03F2203/45696 ,  H03M1/765 ,  H03M1/808

Abstract: An example transconductance circuit is provided in accordance with one embodiment. The transconductance circuit can comprise: an output node; at least one transistor; a variable resistance; and a differential amplifier; wherein the at least one transistor and the variable resistance are in series connection with the output node, an output of the differential amplifier is connected to a control node of the at least one transistor, a first input of the amplifier is responsive to an input signal, and a second input of the amplifier is responsive to a voltage across the variable resistance. Such a circuit may overcome noise problems in transconductance circuits which operate over a wide range of input signals with a fixed resistor in series with the at least one transistor.

Abstract translation: 根据一个实施例提供了示例性跨导电路。 跨导电路可以包括：输出节点; 至少一个晶体管; 可变电阻; 和差分放大器; 其中所述至少一个晶体管和所述可变电阻与所述输出节点串联连接，所述差分放大器的输出端连接到所述至少一个晶体管的控制节点，所述放大器的第一输入端响应于输入信号 并且放大器的第二输入响应可变电阻两端的电压。 这种电路可以克服在具有与至少一个晶体管串联的固定电阻器的宽范围的输入信号上工作的跨导电路中的噪声问题。

公开(公告)号：US20150222288A1

公开(公告)日：2015-08-06

申请号：US14173407

申请日：2014-02-05

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Christopher Peter Hurrell

IPC: H03M1/44 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/442 ,  H03G3/3052 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0678 ,  H03M1/12 ,  H03M1/1295 ,  H03M1/468 ,  H03M1/804

Abstract: Example embodiments of this disclosure can provide an apparatus, a system, and a method of correcting for charge lost from a sampling capacitor as a result of an analog to digital conversion being performed. In an embodiment, there is provided a method of operating an analog to digital converter comprising at least a first sampling capacitor used to sample an input signal, where the method can further comprise a correction step of modifying the voltage across the at least first sampling capacitor, the correction step being performed prior to commencing an acquire phase.

Abstract translation: 本公开的示例性实施例可以提供一种装置，系统和校正由于执行模数转换而从采样电容器损失的电荷的方法。 在一个实施例中，提供了一种操作模数转换器的方法，该方法至少包括用于对输入信号进行采样的第一采样电容器，其中该方法还可以包括校正步骤，该校正步骤修改至少第一采样电容器 ，所述校正步骤在开始获取阶段之前执行。

公开(公告)号：US20150194879A1

公开(公告)日：2015-07-09

申请号：US14147228

申请日：2014-01-03

Applicant: Analog Devices Technology

Inventor： Roger Peppiette ,  Yanfeng Lu ,  Bin Shao ,  Linus Sheng

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract translation: 本应用程序还讨论了升压电路的设备和方法。 在一个示例中，升压电路可以包括第一和第二反相器，共享第一电源节点，并共享第二电源节点，第一电荷转移电容器，被配置为将第一时钟信号耦合到第一反相器输出;第二充电 转移电容器，被配置为将第二时钟信号耦合到第二反相器输出，第二时钟信号与第一时钟信号异相;第一栅极驱动电容器，被配置为将第一时钟信号耦合到第二反相器输入 以及第二栅极驱动电容器，被配置为将所述第二时钟信号耦合到所述第一反相器输入。

公开(公告)号：US09077376B2

公开(公告)日：2015-07-07

申请号：US14214405

申请日：2014-03-14

Applicant: Analog Devices Technology

Inventor： Dennis A. Dempsey

IPC: H03M1/66 ,  H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/76

CPC classification number: H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/682 ,  H03M1/765

Abstract: A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Abstract translation: 描述多串DAC并且包括至少两个DAC级。 每个DAC级包括一串阻抗元件和一个交换网络。 提供控制回路来控制交换网络的Ron，并提供DAC交换网络中交换机的代码相关控制。