公开(公告)号：US20120181677A1

公开(公告)日：2012-07-19

申请号：US13348298

申请日：2012-01-11

申请人： Anthony C. Tsui ,  Hongbo Yang ,  Ming Zhou ,  Weibing Chu ,  Anthony Chia

发明人： Anthony C. Tsui ,  Hongbo Yang ,  Ming Zhou ,  Weibing Chu ,  Anthony Chia

IPC分类号： H01L23/495 ,  H01L23/34

CPC分类号： H01L23/49503 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/06051 ,  H01L2224/1411 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206

摘要： Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

摘要翻译： 本发明的实施例涉及使用冲压来形成半导体器件封装的引线框架上的特征。 在一个实施例中，引线框架（例如销钉）的部分通过冲压移动离开平台的水平面。 在某些实施例中，可以通过冲压将凹口或复杂的横截面轮廓（例如倒角的）赋予销和/或单面胶带的部分。 由这种冲压的横截面轮廓提供的复杂性用于增强引线框架在封装主体的塑料模制件内的机械互锁。 可以单独使用或组合使用诸如选择性电镀和/或形成棕色氧化物保护带以限制管芯附着期间粘合剂材料扩散的其它技术，以便于制造具有这种冲压特征的封装。

公开(公告)号：US07838339B2

公开(公告)日：2010-11-23

申请号：US12191527

申请日：2008-08-14

申请人： Anthony C. Tsui ,  Mohammad Eslamy ,  Anthony Chia ,  Hongbo Yang ,  Ming Zhou ,  Jian Xu

发明人： Anthony C. Tsui ,  Mohammad Eslamy ,  Anthony Chia ,  Hongbo Yang ,  Ming Zhou ,  Jian Xu

IPC分类号： H01L21/82

CPC分类号： H01L23/49575 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/37099

摘要： Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

摘要翻译： 本发明的实施例涉及使用冲压来形成半导体器件封装的引线框架上的特征。 在一个实施例中，引线框架（例如销钉）的部分通过冲压移动离开平台的水平面。 在某些实施例中，可以通过冲压将凹口或复杂的横截面轮廓（例如倒角的）赋予销和/或单面胶带的部分。 由这种冲压的横截面轮廓提供的复杂性用于增强引线框架在封装主体的塑料模制件内的机械互锁。 可以单独使用或组合使用诸如选择性电镀和/或形成棕色氧化物保护带以限制管芯附着期间粘合剂材料扩散的其它技术，以便于制造具有这种冲压特征的封装。

公开(公告)号：US07485498B2

公开(公告)日：2009-02-03

申请号：US11701761

申请日：2007-02-02

申请人： James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

发明人： James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49562 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

摘要翻译： 通过产生用于从设备的接地触点接收下焊线的至少一个补充的下焊垫部分来增强横向导电的半导体器件封装中的空间的有效利用。 补充的底部部分可以占据以前由非整体引线占据的包装的端部或侧面的区域。 通过接收衬底下焊接线，补充的双面部分允许主凹版的更大面积被具有较大面积的模具占据，从而提高了封装的空间效率。

公开(公告)号：US20080217662A1

公开(公告)日：2008-09-11

申请号：US12075814

申请日：2008-03-14

申请人： James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

发明人： James Harnden ,  Allen K. Lam ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

IPC分类号： H01L29/80 ,  H01L23/495

CPC分类号： H01L23/49562 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.

摘要翻译： 通过产生用于从设备的接地触点接收下焊线的至少一个补充的下焊垫部分来增强横向导电的半导体器件封装中的空间的有效利用。 补充的底部部分可以占据以前由非整体引线占据的包装的端部或侧面的区域。 通过接收衬底下焊接线，补充的双面部分允许主凹版的更大面积被具有较大面积的模具占据，从而提高了封装的空间效率。

公开(公告)号：US20080142936A1

公开(公告)日：2008-06-19

申请号：US12070663

申请日：2008-02-19

申请人： Hamza Yilmaz ,  Anthony Chia ,  Seishi Fujimaki ,  Xiaoguang Zeng

发明人： Hamza Yilmaz ,  Anthony Chia ,  Seishi Fujimaki ,  Xiaoguang Zeng

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L21/6835 ,  H01L21/4828 ,  H01L21/568 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

公开(公告)号：US20080135991A1

公开(公告)日：2008-06-12

申请号：US11609706

申请日：2006-12-12

申请人： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Teng Hui ,  Hongbo Yang ,  Zhou Ming ,  Anthony C. Tsui

发明人： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Teng Hui ,  Hongbo Yang ,  Zhou Ming ,  Anthony C. Tsui

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49572 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16245 ,  H01L2224/37124 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

摘要： Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with a supported die through electrically conducting bumps or balls. By eliminating the need for a separate diepad and lateral isolation between an edge of the diepad and adjacent non-integral leads or pins, embodiments of packages fabricated by bump on leadframe (BOL) processes in accordance with embodiments of the present invention increase the space available to the die for a given package footprint. Embodiments of the present invention may also permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint.

摘要翻译： 本发明的实施例涉及具有封装的引线框的半导体器件封装，其通过导电凸块或球与支撑的裸片电连通。 通过消除对单板的边缘和相邻的非整体引线或引脚之间的单独的双面和侧向隔离的需要，根据本发明的实施例的通过引线框架上的凸起（BOL）工艺制造的封装的实施例增加了可用的空间 给模具一个给定的封装足迹。 本发明的实施例还可以允许多个管芯和/或多个无源器件占据以前由diepad消耗的封装中的空间。 结果是灵活的封装过程，允许在传统的小型JEDEC规定的占地面积中，完整子系统所需的管芯和技术的组合。

公开(公告)号：US07382044B1

公开(公告)日：2008-06-03

申请号：US11409188

申请日：2006-04-21

申请人： Hamza Yilmaz ,  Anthony Chia ,  Seishi Fujimaki ,  Xiaoguang Zeng

发明人： Hamza Yilmaz ,  Anthony Chia ,  Seishi Fujimaki ,  Xiaoguang Zeng

IPC分类号： H01L23/495

CPC分类号： H01L21/6835 ,  H01L21/4828 ,  H01L21/568 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

摘要翻译： 根据本发明的实施例涉及用于半导体器件的封装的制造，特别涉及使用电镀技术在金属引线框架的表面上形成特征。 根据一个实施例，电镀用于制造成形为保持可靠地封装在包装的塑料模制件内的非整体销部分。 根据另一个实施例，可以使用电镀来在引线框架的下侧上制造凸起，用于升高PC板上的封装，从而保持用于将凹版固定到PC板的焊球的圆形。 根据另一个实施例，电镀可以用于在双面胶带的上表面上制造凸起的图案，以确保用于将模具固定到单面胶带上的粘合剂的均匀铺展，从而确保模具在包装内的水平姿态。

公开(公告)号：US20070130759A1

公开(公告)日：2007-06-14

申请号：US11416994

申请日：2006-05-02

申请人： James Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang

发明人： James Harnden ,  Anthony Chia ,  Liming Wong ,  Hongbo Yang

IPC分类号： H01L21/00

CPC分类号： H01L23/3107 ,  H01L21/4821 ,  H01L23/49534 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01046 ,  H01L2924/01079 ,  Y10T29/49117 ,  Y10T29/49121

摘要： A leadframe having raised features for use a semiconductor device package, is fabricated by bonding together at least two metal layers. A first metal layer may define the lateral dimensions of the leadframe, including any diepad and leads. A second metal layer bonded to the first metal layer, may define the raised features of the leadframe, such as steps for physically securing the leadframe within the package body. The multiple metal layers may be bonded together by a number of possible techniques, including but not limited to ultrasonic welding, soft soldering, or the use of epoxy. Prior to or after bonding, one or more of the metal layers may be coined or stamped to form additional features such as offsets or channels.

摘要翻译： 通过将至少两个金属层结合在一起而制造具有用于使用半导体器件封装的凸起特征的引线框架。 第一金属层可以限定引线框架的横向尺寸，包括任何凹凸和引线。 结合到第一金属层的第二金属层可以限定引线框的凸起特征，例如用于物理地将引线框固定在封装主体内的步骤。 多个金属层可以通过多种可能的技术结合在一起，包括但不限于超声波焊接，软焊接或使用环氧树脂。 在粘合之前或之后，一个或多个金属层可以被压印或冲压以形成诸如偏移或通道的附加特征。

公开(公告)号：USD505122S1

公开(公告)日：2005-05-17

申请号：US29173668

申请日：2003-01-03

申请人： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing ,  Allen K. Lam

设计人： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing ,  Allen K. Lam

公开(公告)号：USD491900S1

公开(公告)日：2004-06-22

申请号：US29172802

申请日：2002-12-17

申请人： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing

设计人： James Harnden ,  Richard K. Williams ,  Anthony Chia ,  Chu Weibing