公开(公告)号：US20110261979A1

公开(公告)日：2011-10-27

申请号：US12978577

申请日：2010-12-26

Applicant: Bin YANG ,  Rui Zhang

Inventor： Bin YANG ,  Rui Zhang

IPC: H04R1/00 ,  G10K13/00

CPC classification number: H04R19/005 ,  H04R7/04 ,  H04R7/18 ,  H04R2201/003 ,  H04R2307/207 ,  H04R2499/11

Abstract: A diaphragm is disclosed. The diaphragm includes a vibrating member, a projection extruding from a periphery of the vibrating member, a supporting member surrounding the vibrating member. A first gap is formed between the vibrating member and the supporting member. The supporting member includes a supporting girder surrounding and separated from the projection. A torsion girder is connected to the projection and a fixing girder is parallel to the torsion girder. A second gap is defined between the fixing girder and the torsion girder.

Abstract translation: 公开了一种隔膜。 隔膜包括振动构件，从振动构件的周边挤出的突起，围绕振动构件的支撑构件。 在振动构件和支撑构件之间形成第一间隙。 支撑构件包括围绕并与突起分离的支撑梁。 扭矩梁连接到突出部，并且固定梁平行于扭矩梁。 在固定梁和扭矩梁之间限定了第二间隙。

公开(公告)号：US20110235829A1

公开(公告)日：2011-09-29

申请号：US12978574

申请日：2010-12-26

Applicant: Bin YANG ,  Rui Zhang

Inventor： Bin YANG ,  Rui Zhang

IPC: H04R11/04 ,  H04R7/00

CPC classification number: H04R19/04

Abstract: Disclosed is a diaphragm includes a vibrating member, a plurality of supporting members extending from a periphery of the vibrating member along a direction away from a center of the diaphragm, and a plurality of separating portions each located between two adjacent supporting members. Each of the supporting members defines a first beam, a second beam, and at least one slit between the first and second beams.

Abstract translation: 公开了一种隔膜，包括振动部件，沿着远离振动膜中心的方向从振动部件的周边延伸的多个支撑部件，以及分别设置在两个相邻支撑部件之间的多个分离部。 每个支撑构件限定第一梁，第二梁和在第一和第二梁之间的至少一个狭缝。

公开(公告)号：US20110230017A1

公开(公告)日：2011-09-22

申请号：US12726736

申请日：2010-03-18

Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

IPC: H01L21/336

CPC classification number: H01L29/7839 ,  H01L29/78654

Abstract: A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A raised semiconductor material is selectively formed on the first semiconductor layer adjacent to the gate structure. The raised semiconductor material is converted into Schottky source and drain regions composed of a metal semiconductor alloy. A non-reacted semiconductor material is present between the Schottky source and drain regions and the dielectric layer.

Abstract translation: 提供一种制造肖特基场效应晶体管的方法，其包括提供具有覆盖在电介质层上的至少第一半导体层的衬底，其中第一半导体层具有小于10.0nm的厚度。 栅极结构直接形成在第一半导体层上。 凸起的半导体材料选择性地形成在与栅极结构相邻的第一半导体层上。 凸起的半导体材料被转换成由金属半导体合金构成的肖特基源极和漏极区域。 在肖特基源极和漏极区域与电介质层之间存在未反应的半导体材料。

公开(公告)号：US20110227157A1

公开(公告)日：2011-09-22

申请号：US12726889

申请日：2010-03-18

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/78618 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

Abstract translation: 在诸如极薄的SOI（ETSOI）衬底的SOI衬底上形成半导体，具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层（例如嵌入硅锗（eSiGe））的半导体器件。 实施例包括形成SOI衬底，在SOI衬底上外延形成含硅层，并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后，去除栅电极和下面的含硅层，并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失，从而增加延伸厚度并降低延伸电阻。

公开(公告)号：US20110224099A1

公开(公告)日：2011-09-15

申请号：US13046531

申请日：2011-03-11

Applicant: David G. Gorenstein ,  Bruce A. Luxon ,  Norbert Herzog ,  Xian Bin Yang

Inventor： David G. Gorenstein ,  Bruce A. Luxon ,  Norbert Herzog ,  Xian Bin Yang

IPC: C40B40/06

CPC classification number: C07H21/00 ,  B01J2219/00378 ,  B01J2219/00387 ,  B01J2219/00497 ,  B01J2219/005 ,  B01J2219/00529 ,  B01J2219/00585 ,  B01J2219/0059 ,  B01J2219/00592 ,  B01J2219/00596 ,  B01J2219/00608 ,  B01J2219/0061 ,  B01J2219/00612 ,  B01J2219/00626 ,  B01J2219/00637 ,  B01J2219/00641 ,  B01J2219/00648 ,  B01J2219/00659 ,  B01J2219/00689 ,  B01J2219/00707 ,  B01J2219/00722 ,  C07B2200/11 ,  C12N15/1048 ,  C40B20/04 ,  C40B40/06 ,  C40B40/08 ,  C40B60/14 ,  G01N33/6803 ,  G01N33/6851

Abstract: The present invention includes composition and methods for making and using a combinatorial library having two or more beads, wherein attached to each bead is a unique nucleic acid aptamer that have disposed thereon a unique sequence. The library aptamers may be attached covalently to the one or more beads, which may be polystyrene beads. The aptamers may include phosphorothioate, phosphorodithioate and/or methylphosphonate linkages and may be single or double stranded DNA, RNA or even PNAs.

Abstract translation: 本发明包括用于制备和使用具有两个或多个珠的组合文库的组合物和方法，其中连接到每个珠粒是在其上设置有唯一序列的唯一核酸适体。 文库适体可以共价连接到一个或多个珠，其可以是聚苯乙烯珠。 适体可以包括硫代磷酸酯，二硫代磷酸酯和/或甲基膦酸酯键，并且可以是单链或双链DNA，RNA或甚至PNA。

公开(公告)号：US20110198694A1

公开(公告)日：2011-08-18

申请号：US12707150

申请日：2010-02-17

Applicant: Man Fai NG ,  Bin YANG

Inventor： Man Fai NG ,  Bin YANG

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/76267 ,  H01L21/823878 ,  H01L29/66772

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract translation: 提供了用于制造在绝缘材料区域内具有阻挡区域的半导体器件的方法和装置，导致从绝缘材料区域的脱气路径。 一种方法包括在靠近半导体材料的隔离区域的绝缘材料内形成阻挡区域，并形成覆盖半导体材料的隔离区域的栅极结构。 阻挡区域与半导体材料的隔离区域相邻，导致绝缘材料内的除气路径。

公开(公告)号：US07994014B2

公开(公告)日：2011-08-09

申请号：US12249570

申请日：2008-10-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

Abstract translation: 所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。 根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。 沟道区形成在半导体材料层中，栅极结构下方的沟道区。 半导体器件还包括半导体材料层中的源区和漏区，其中沟道区位于源区和漏区之间。 此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

公开(公告)号：US07981903B2

公开(公告)日：2011-07-19

申请号：US12671960

申请日：2008-08-06

Applicant: Stanley Dawes Chamberlain ,  Felix Deanda, Jr. ,  Roseanne Gerding ,  Masaichi Hasegawa ,  Kevin Kuntz ,  Huangshu Lei ,  Yasushi Miyazaki ,  Naohiko Nishigaki ,  Samarjit Patnaik ,  Aniko Redman ,  John Brad Shotwell ,  Kirk Stevens ,  Joseph Wilson ,  Bin Yang

Inventor： Stanley Dawes Chamberlain ,  Felix Deanda, Jr. ,  Roseanne Gerding ,  Masaichi Hasegawa ,  Kevin Kuntz ,  Huangshu Lei ,  Yasushi Miyazaki ,  Naohiko Nishigaki ,  Samarjit Patnaik ,  Aniko Redman ,  John Brad Shotwell ,  Kirk Stevens ,  Joseph Wilson ,  Bin Yang

IPC: A01N43/90 ,  A61K31/519 ,  C07D487/00

CPC classification number: C07D487/04 ,  C07D487/14

Abstract: Novel pyrrolopyrimidines as shown in formula (I): and pharmaceutically acceptable derivatives thereof. The compounds are useful in the inhibition of IGF-1R.

Abstract translation: 式（I）所示的新型吡咯并嘧啶及其药学上可接受的衍生物。 该化合物可用于抑制IGF-1R。

公开(公告)号：US07939852B2

公开(公告)日：2011-05-10

申请号：US12176835

申请日：2008-07-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L31/0328

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US20110090773A1

公开(公告)日：2011-04-21

申请号：US12854145

申请日：2010-08-10

Applicant: Chih-Ching Yu ,  Pi-Hai Liu ,  Yu-Hsuan Lin ,  Ying-Feng Huang ,  Yuh Cheng ,  Jin-Bin Yang

Inventor： Chih-Ching Yu ,  Pi-Hai Liu ,  Yu-Hsuan Lin ,  Ying-Feng Huang ,  Yuh Cheng ,  Jin-Bin Yang

IPC: G11B20/10

CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10296 ,  G11B20/1037 ,  G11B20/10425 ,  G11B2220/2537

Abstract: An apparatus for generating Viterbi-processed data using an input signal obtained from reading an optical disc includes a Viterbi decoding unit and a control circuit. The Viterbi decoding unit is arranged to process the input signal and generate the Viterbi-processed data. In addition, the control circuit is arranged to control at least one component of the apparatus based upon at least one signal within the apparatus. Additionally, the component includes a phase locked loop (PLL) processing unit, an equalizer, and/or the Viterbi decoding unit. An associated apparatus including an equalizer and a Viterbi module is further provided. An associated apparatus including a Viterbi decoding unit and a control circuit is also provided. An associated apparatus including an equalizer, at least one offset/gain controller, and a Viterbi module is further provided. An associated apparatus including an equalizer, a Viterbi module, and a peak/bottom/central (PK/BM/DC) detector is also provided.

Abstract translation: 使用从读取光盘获得的输入信号来产生维特比处理数据的装置包括维特比解码单元和控制电路。 维特比解码单元被布置成处理输入信号并生成维特比处理的数据。 此外，控制电路被布置成基于装置内的至少一个信号来控制装置的至少一个部件。 此外，该组件包括锁相环（PLL）处理单元，均衡器和/或维特比解码单元。 还提供了包括均衡器和维特比模块的相关设备。 还提供了包括维特比解码单元和控制电路的相关设备。 还提供了包括均衡器，至少一个偏移/增益控制器和维特比模块的相关设备。 还提供了包括均衡器，维特比模块和峰值/底部/中央（PK / BM / DC）检测器的相关设备。