公开(公告)号：US07927993B2

公开(公告)日：2011-04-19

申请号：US12344375

申请日：2008-12-26

申请人： Brian K. Kirkpatrick

发明人： Brian K. Kirkpatrick

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02087 ,  H01L21/02068 ,  H01L21/0209 ,  H01L21/32134 ,  H01L21/823807 ,  H01L21/823828

摘要： A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface. The selective removing includes a first wet etch that etches the metal gate electrode material highly selectively as compared to the semiconductor, wherein the first wet etch includes a strong oxidizing acid, a weak acid that generally include an organic acid, and a fluoride. The fabrication of the IC including is completed including forming at least one metal interconnect layer after the selectively removing step.

摘要翻译： 一种制造CMOS集成电路（IC）的方法包括提供包括具有顶侧半导体表面，斜面半导体表面和背面半导体表面的晶片的半导体。 至少在顶侧半导体表面上形成栅介质层。 包括至少第一金属的包括栅电极材料的金属沉积在顶侧半导体表面上的栅介质层上，以及斜面半导体表面的至少一部分和背侧半导体表面的至少一部分上。 选择性地去除包括斜面半导体表面上的栅电极材料和背面半导体表面的金属，以形成基本上第一金属自由斜面和背面，同时保护顶侧半导体表面上的金属栅电极材料。 选择性去除包括与半导体相比高度选择性地蚀刻金属栅电极材料的第一湿蚀刻，其中第一湿蚀刻包括强氧化酸，通常包含有机酸的弱酸和氟化物。 完成IC的制造包括在选择性除去步骤之后形成至少一个金属互连层。

公开(公告)号：US20110031557A1

公开(公告)日：2011-02-10

申请号：US12908140

申请日：2010-10-20

申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

公开(公告)号：US20100261353A1

公开(公告)日：2010-10-14

申请号：US12757665

申请日：2010-04-09

申请人： Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

发明人： Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

IPC分类号： H01L21/465 ,  H01L21/46

CPC分类号： H01L22/20 ,  G03F7/70616 ,  G03F7/70783 ,  G03F7/70875 ,  H01L22/12

摘要： A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.

摘要翻译： 一种用于在光刻图案级别之间控制晶片的平坦度的方法。 在晶片的顶侧半导体表面上进行第一光刻步骤。 获得晶片的参考曲率信息。 参考曲率不是平面的。 执行至少一个处理步骤，其导致相对于参考曲率改变的曲率。 获得用于晶片的变化的曲率信息。 修改了晶片底部表面上的应力，减小了改变的曲率和参考曲率之间的差异。 在存在改性应力分布的同时，在顶侧半导体表面上进行第二光刻步骤。

公开(公告)号：US20100248440A1

公开(公告)日：2010-09-30

申请号：US12731913

申请日：2010-03-25

申请人： Brian K. Kirkpatrick ,  Deborah J. Riley

发明人： Brian K. Kirkpatrick ,  Deborah J. Riley

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L29/6653 ,  H01L29/6656

摘要： A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.

摘要翻译： 一种在半导体表面上去除氮化硅以形成浅结的方法。 侧壁间隔物沿着栅堆叠的侧壁形成，其一起限定轻掺杂漏极（LDD）区域或源极/漏极（S / D）区域。 侧壁间隔物，LDD区域和S / D区域中的至少一个包括暴露的氮化硅层。 LDD或S / D区域包括直接形成在半导体表面上的保护电介质层。 离子注入使用侧壁间隔物作为植入物掩模来植入LDD区域或S / D区域。 暴露的氮化硅层被选择性地去除，其中当侧壁间隔物包括暴露的氮化硅层时的保护电介质层，或者当LDD或S / D区域包括 暴露的氮化硅层，在选择性去除期间由于蚀刻而保护LDD或S / D区域免受掺杂剂损失。

公开(公告)号：US20100167519A1

公开(公告)日：2010-07-01

申请号：US12344421

申请日：2008-12-26

申请人： BRIAN K. KIRKPATRICK ,  JINHAN CHOI ,  DEBORAH J. RILEY

发明人： BRIAN K. KIRKPATRICK ,  JINHAN CHOI ,  DEBORAH J. RILEY

IPC分类号： H01L21/3205 ,  H01L21/461

CPC分类号： H01L21/02071 ,  H01L21/31111 ,  H01L29/517 ,  H01L29/78 ,  Y10S438/906

摘要： A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.

摘要翻译： 制造CMOS集成电路（IC）的方法包括提供具有半导体表面的衬底的步骤。 在半导体表面上形成包括金属栅电极在包含高k电介质层的金属上的栅叠层。 使用干蚀刻来图案化栅极堆叠以限定具有金属栅电极的暴露侧壁的图案化栅电极堆叠。 干蚀刻形成后蚀刻残留物，其中一些沉积在基底上。 包括图案化的栅极电极堆叠的衬底暴露于溶液清洁序列，其包括包括第一酸和氟化物的第一清洁步骤，用于去除至少一部分后蚀刻残留物，其中第一清洁步骤具有高选择性以避免 蚀刻金属栅电极的暴露的侧壁。 第一次清洁后的第二次清洁基本上由氟化物组成，其除去半导体表面上残留的高k材料。

公开(公告)号：US20090098702A1

公开(公告)日：2009-04-16

申请号：US12253095

申请日：2008-10-16

申请人： Brian K. Kirkpatrick ,  Weize Xiong ,  Steven L. Prins

发明人： Brian K. Kirkpatrick ,  Weize Xiong ,  Steven L. Prins

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/3086 ,  H01L21/76224

摘要： A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation sidewall spacers reduce the exposed substrate width during the subsequent STI trench etch process, leading to a reduced STI trench width. A method of forming the isolation sidewall spacers of a material that is easily removed from the isolation hardmask to provide an exposed shoulder width on the substrate defined by the sidewall thickness is also disclosed.

摘要翻译： 公开了一种使用隔离硬掩模上的侧壁间隔来形成减小宽度的STI场氧化物元件以减少STI沟槽宽度的方法。 通过在隔离硬掩模上沉积间隔物材料的共形层并执行各向异性蚀刻来形成隔离侧壁间隔物。 隔离侧壁间隔物在随后的STI沟槽蚀刻工艺期间减少暴露的衬底宽度，导致减小的STI沟槽宽度。 还公开了一种形成隔离侧壁间隔物的方法，该材料容易从隔离硬掩模中移除，以在由侧壁厚度限定的衬底上提供暴露的肩宽。

公开(公告)号：US07186651B2

公开(公告)日：2007-03-06

申请号：US10697676

申请日：2003-10-30

申请人： Joe G. Tran ,  Chad J. Kaneshige ,  Brian K. Kirkpatrick

发明人： Joe G. Tran ,  Chad J. Kaneshige ,  Brian K. Kirkpatrick

IPC分类号： H01L21/302

CPC分类号： B24B37/26 ,  H01L21/31053

摘要： A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.

摘要翻译： 描述了通过化学机械抛光工艺从半导体晶片的表面去除材料的方法。 该方法使用其上形成有线图案的抛光垫。 该图案包括有序间隔的开槽面积和无凹槽的区域。 该方法结合了晶片的表面形貌，待去除材料的性质和抛光垫表面上的可用凹槽图案的信息，以产生半导体晶片的部分驻留时间花费的处理配方 在化学机械抛光过程中在抛光垫的开槽和未开槽区域预先确定。

公开(公告)号：US06797644B2

公开(公告)日：2004-09-28

申请号：US09906515

申请日：2001-07-16

申请人： Victor Watt ,  Beth Walden ,  Brian K. Kirkpatrick ,  Edmund G. Russell

发明人： Victor Watt ,  Beth Walden ,  Brian K. Kirkpatrick ,  Edmund G. Russell

IPC分类号： H01I2131

CPC分类号： H01L21/28185 ,  C23C8/10 ,  C23C8/16 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/3003 ,  H01L21/31662 ,  H01L21/823807

摘要： Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place normally and the silicon-silicon oxide interface is concurrently saturated with deuterium. Saturating the interface with deuterium reduces the interface trap density thereby reducing channel hot carrier degradation.

摘要翻译： 在流氧化期间使用氘氧形成氧化蒸汽。 由于氘与氢化学相似，因此氧化过程正常进行，硅氧化硅界面同时饱和氘。 用氘饱和界面会降低界面陷阱密度，从而减少通道热载流子的退化。

公开(公告)号：US20160233132A9

公开(公告)日：2016-08-11

申请号：US13427062

申请日：2012-03-22

申请人： BRIAN K. KIRKPATRICK ,  AMITABH JAIN

发明人： BRIAN K. KIRKPATRICK ,  AMITABH JAIN

IPC分类号： H01L29/772 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/161 ,  H01L21/336 ,  H01L21/311

CPC分类号： H01L27/092 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823864 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/778 ,  H01L29/7833

摘要： A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

公开(公告)号：US08450221B2

公开(公告)日：2013-05-28

申请号：US12850097

申请日：2010-08-04

申请人： Brian K. Kirkpatrick ,  James Joseph Chambers

发明人： Brian K. Kirkpatrick ,  James Joseph Chambers

IPC分类号： H01L21/00

CPC分类号： H01L29/518 ,  H01L21/28044 ,  H01L21/28202 ,  H01L29/78

摘要： A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

摘要翻译： 形成具有至少一个MOS器件的集成电路（IC）的方法包括在硅表面上形成SiON栅介质层。 在SiON栅极层上沉积栅电极层，然后构图形成栅叠层。 通过图案化揭示了暴露的栅极电介质侧壁。 在暴露的SiON侧壁上形成补充的氧化硅层，然后氮化。 氮化后，氮化退火（PNA）形成包括N增强SiON侧壁的退火的N增强SiON栅极电介质层，其中沿着恒定厚度的线，N增强SiON侧壁处的N浓度> 大部分退火的N增强SiON栅极层-2原子％。 形成栅极堆叠的相对侧上的源极和漏极区域以限定栅极叠层下方的沟道区域。