公开(公告)号：US20070269948A1

公开(公告)日：2007-11-22

申请号：US11436884

申请日：2006-05-19

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A two-bits-per-cell flash memory cell is based on a localized trapping storage mechanism. The memory cell may be programmed via a hot hole injection mechanism and erased via a Fowler-Nordheim electron tunneling mechanism. The memory cells are arranged according to a virtual-ground wiring scheme. Gate structures of the memory cells are arranged in columns, and the widths of the columns are essentially equal to the distance between the columns. Bit lines elongate in pairs between the columns of memory cells and connect corresponding impurity regions being associated to one of the columns of memory cells. Separation devices separating the bit lines of each pair of bit lines are formed symmetrically to the edges of the neighboring columns of memory cells. Program cross-talk issues, concerning memory cells sharing the same bit line, may be avoided while memory cell size remains essentially unaffected.

Abstract translation: 每单元两位闪存单元基于局部捕获存储机制。 可以通过热空穴注入机构对存储单元进行编程，并通过Fowler-Nordheim电子隧穿机构擦除。 存储单元根据虚拟接地布线方案布置。 存储器单元的栅极结构被布置成列，并且列的宽度基本上等于列之间的距离。 位线在存储器单元的列之间成对延伸，并且连接与存储器单元的列之一相关联的相应杂质区。 分离每对位线的位线的分离装置对称地形成存储单元的相邻列的边缘。 关于共享相同位线的存储器单元的程序串扰问题可能被避免，而存储单元大小基本上不受影响。

公开(公告)号：US20070243707A1

公开(公告)日：2007-10-18

申请号：US11686501

申请日：2007-03-15

Applicant: Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch ,  Ludovic Lattard ,  Martin Roessiger ,  Mirko Vogt

Inventor： Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert ,  Lothar Bauch ,  Stefan Blawid ,  Manuela Gutsch ,  Ludovic Lattard ,  Martin Roessiger ,  Mirko Vogt

IPC: H01L21/44 ,  G03F1/00 ,  H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/0332 ,  H01L27/105 ,  H01L27/112

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract translation: 用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料 碳层顶部和设置在第一层顶部的硅层。 图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

公开(公告)号：US20060244024A1

公开(公告)日：2006-11-02

申请号：US11118768

申请日：2005-05-02

Applicant: Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

Inventor： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

IPC: H01L29/94

CPC classification number: H01L27/10876 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891

Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

公开(公告)号：US06956260B2

公开(公告)日：2005-10-18

申请号：US10463019

申请日：2003-06-17

Applicant: Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

Inventor： Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10891

Abstract: In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.

Abstract translation: 在半导体存储器中，特别是DRAM，其存储单元在由衬底材料形成的垂直焊盘处具有垂直晶体管，栅电极形成为围绕焊盘运行的间隔件。 相邻存储单元的栅电极通常必须追溯地连接以形成字线。 已知用相邻的焊盘之间的空间填充氧化物，结果是间隔件直接形成为字线，而仅覆盖焊盘的两个侧壁。 并联连接的两个晶体管形成在这些侧壁而不是单个晶体管，因为栅电极不会绕着焊盘运行。 本发明提出一种半导体存储器的制造方法，其中，由字线覆盖焊盘的四个侧壁，同时通过字线将相邻存储单元的焊盘相互连接。

公开(公告)号：US06919255B2

公开(公告)日：2005-07-19

申请号：US10630373

申请日：2003-07-30

Applicant: Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

Inventor： Albert Birner ,  Matthias Goldbach ,  Thomas Hecht ,  Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Dirk Manger ,  Andreas Orth

IPC: H01L27/108 ,  H01L21/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/1087 ,  H01L29/66181 ,  H01L29/945

Abstract: A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Abstract translation: 一种制造半导体沟槽结构的方法包括在半导体衬底中形成沟槽并用填充物填充沟槽。 具有第一最高温度的第一热处理固化填料。 从沟槽的上部区域移除填料至达边界表面限定了一个环形区域。 在具有不显着高于第一最高温度的第二最高温度的第二热处理中，衬套沉积在套环区域和边界表面上。 将衬垫从边界表面移除，从而暴露填料。 然后从沟槽的下部区域去除填料。

公开(公告)号：US20050032309A1

公开(公告)日：2005-02-10

申请号：US10850960

申请日：2004-05-21

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/1087

Abstract: A memory cell has a vertical construction of a capacitor and a vertical FET arranged above the latter which can be produced with a lower outlay and in a technologically more reliable fashion. This is achieved by virtue of the fact that two first trenches running parallel and having a first depth are etched in the semiconductor substrate. Between the trenches is formed a web, which is connected to the semiconductor substrate at its narrow sides and which is severed at its underside and is separated from the semiconductor substrate. The suspended web is then provided with a closed dielectric. After a filling, the FET is applied and connected to the web as memory node.

Abstract translation: 存储单元具有垂直构造的电容器和布置在其上方的垂直FET，其可以以较低的开销和技术上更可靠的方式产生。 这是通过在半导体衬底中蚀刻平行且具有第一深度的两个第一沟槽来实现的。 在沟槽之间形成网状物，该网状物在其窄边连接到半导体衬底，并且在其下侧被切断并与半导体衬底分离。 然后，悬挂的网带有封闭的电介质。 填充后，施加FET并将其连接到作为存储器节点的网。

公开(公告)号：US20090309152A1

公开(公告)日：2009-12-17

申请号：US12137388

申请日：2008-06-11

Applicant: Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

Inventor： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Abstract translation: 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

公开(公告)号：US07339224B2

公开(公告)日：2008-03-04

申请号：US10482154

申请日：2002-06-12

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L29/94

CPC classification number: H01L27/10861 ,  H01L27/10829 ,  H01L27/10867 ,  H01L29/66181

Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30″) provided in the trench (2) as second electrode. Above the conducting metallic filling material (30″) a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.

Abstract translation: 本发明涉及一种沟槽电容器，特别是用于半导体存储器单元中的沟槽电容器，其包括在衬底（1）中实施的沟槽（2），设置在衬底（1）中的第一区域（1a），如 第一电容器电极，作为电容器电介质的沟槽壁上的介电层（10）和作为第二电极设置在沟槽（2）中的金属填充材料（30“）。 在导电金属填充材料（30“）上方，介电填充材料（35）在沟槽（2）中设置有用于机械张力的空腔（40）。 本发明还涉及相应的生产方法。

公开(公告)号：US20070254442A1

公开(公告)日：2007-11-01

申请号：US11414553

申请日：2006-05-01

Applicant: Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

Inventor： Dirk Manger ,  Jyoti Gupta ,  Christoph Ludwig ,  Hans Lindemann

IPC: H01L21/336

CPC classification number: H01L21/28247 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.

Abstract translation: 选择性地在垂直装置的垂直侧壁上生长的生长材料在垂直装置的基本上垂直的侧壁上形成侧壁间隔物，其设置在半导体衬底的水平衬底表面上。 可以在垂直装置的垂直侧壁上设置间隔物种子衬垫，以控制选择性生长。 垂直装置可以是场效应晶体管（FET）的栅电极。 利用选择性地生长的侧壁间隔物，FET的重掺杂接触区域可以与栅电极精确地间隔开。 重掺杂的接触区域与栅电极的距离不取决于栅电极的高度。 可以实现重掺杂接触区域和栅电极之间超过150nm的距离，以便于例如DMOS器件的形成。

公开(公告)号：US20070037345A1

公开(公告)日：2007-02-15

申请号：US11203404

申请日：2005-08-15

Applicant: Dirk Manger

Inventor： Dirk Manger

IPC: H01L21/8242

CPC classification number: H01L27/10855 ,  H01L27/10817 ,  H01L28/91

Abstract: A method of forming a memory cell array including a plurality of memory cells includes patterning isolation trenches on a semiconductor substrate and filling with an insulating material to define active area lines. In particular, the isolation trenches are patterned as straight lines, resulting in the active area lines being formed as straight lines. After forming word lines incorporating a plurality of gate electrodes, isolation grooves are formed by etching the semiconductor substrate material using the gate electrodes as an etching mask. The active area segments are isolated from each other by a self-aligned etching step. Thereafter, the transistors are completed by defining the first and second source/drain regions, and the remaining parts of the memory cells, in particular, the capacitor contacts, the bit lines and the storage capacitors are formed.

Abstract translation: 形成包括多个存储单元的存储单元阵列的方法包括：图案化半导体衬底上的隔离沟槽并填充绝缘材料以限定有源面积线。 特别地，隔离沟槽被图案化为直线，导致有源面积线形成为直线。 在形成包含多个栅电极的字线之后，通过使用栅电极作为蚀刻掩模蚀刻半导体衬底材料来形成隔离沟槽。 有源区段通过自对准蚀刻步骤彼此隔离。 此后，通过限定第一和第二源/漏区来完成晶体管，并且形成存储单元的其余部分，特别是电容器触点，位线和存储电容器。