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    SEMICONDUCTOR DEVICE HAVING TRI-GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    31.
    发明申请
    SEMICONDUCTOR DEVICE HAVING TRI-GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    具有三极晶体管的半导体器件及其制造方法

    公开(公告)号：US20150041913A1

    公开(公告)日：2015-02-12

    申请号：US14192074

    申请日：2014-02-27

    Applicant: Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

    Inventor： Tae-Hyun AN ,  Toshiro NAKANISHI ,  Gab-Jin NAM ,  Jong-Ho LEE

    IPC: H01L29/78 ,  H01L27/092

    CPC classification number: H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

    Abstract: A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

    Abstract translation: 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING A RECESSED-CHANNEL
    32.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING A RECESSED-CHANNEL 有权
    制造具有接收通道的半导体器件的方法

    公开(公告)号：US20110201168A1

    公开(公告)日：2011-08-18

    申请号：US12984176

    申请日：2011-01-04

    Applicant: Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    Inventor： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

    IPC: H01L21/336

    CPC classification number: H01L27/10876 ,  H01L29/66628

    Abstract: A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

    Abstract translation: 根据示例实施例的方法包括在衬底中形成隔离区域，所述隔离区限定活性区域。 去除有源区域和隔离区域的期望区域，从而形成凹槽沟槽到期望的深度。 凹槽沟槽是雾化的，以具有与活性区域接触的第一区域和与隔离区域接触的第二区域。 凹槽沟槽的底面的宽度小于其顶面的宽度。 有源区域和隔离区域被退火以提高凹槽通道沟槽的底面。 第一区域的底面的面积增加。 第一区域的底面的深度减小。

    Complementary metal-oxide-semiconductor transistor including multiple gate conductive layers and method of manufacturing the same
    33.
    发明授权
    Complementary metal-oxide-semiconductor transistor including multiple gate conductive layers and method of manufacturing the same 失效
    包括多个栅极导电层的互补金属氧化物半导体晶体管及其制造方法

    公开(公告)号：US07646067B2

    公开(公告)日：2010-01-12

    申请号：US11891337

    申请日：2007-08-10

    Applicant: Gab-Jin Nam ,  Myoung-Bum Lee

    Inventor： Gab-Jin Nam ,  Myoung-Bum Lee

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L23/62

    CPC classification number: H01L21/823842 ,  Y10S257/914

    Abstract: A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.

    Abstract translation: 公开了CMOS晶体管和制造CMOS晶体管的方法。 NMOS晶体管形成在半导体衬底的第一区域上。 PMOS晶体管形成在半导体衬底的第二区域上。 NMOS晶体管包括第一栅极导电层。 PMOS晶体管包括第二栅极导电层。 第一栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.0eV至约4.3eV的功函数。 第三栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.7eV至约5.0eV的功函数。

    Semiconductor memory device and method of manufacturing the semiconductor memory device
    34.
    发明授权
    Semiconductor memory device and method of manufacturing the semiconductor memory device 有权
    半导体存储器件及半导体存储器件的制造方法

    公开(公告)号：US07338863B2

    公开(公告)日：2008-03-04

    申请号：US11311143

    申请日：2005-12-20

    Applicant: Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    Inventor： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

    Abstract: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

    Abstract translation: 本发明的示例实施例公开了一种非易失性半导体存储器件，其可以包括具有增强介电常数的介电层。 可以在衬底上依次形成隧道氧化物层图案和浮栅。 可以使用脉冲激光沉积工艺在浮栅上形成包括掺杂有III族过渡金属的金属氧化物的电介质层图案。 具有增加的介电常数的电介质层图案可以由掺杂有过渡金属如钪，钇或镧的金属氧化物形成。

    Complementary metal-oxide-semiconductor transistor and method of manufacturing the same
    35.
    发明申请
    Complementary metal-oxide-semiconductor transistor and method of manufacturing the same 失效
    互补金属氧化物半导体晶体管及其制造方法

    公开(公告)号：US20080042213A1

    公开(公告)日：2008-02-21

    申请号：US11891337

    申请日：2007-08-10

    Applicant: Gab-Jin Nam ,  Myoung-Bum Lee

    Inventor： Gab-Jin Nam ,  Myoung-Bum Lee

    IPC: H01L21/8238 ,  H01L29/94

    CPC classification number: H01L21/823842 ,  Y10S257/914

    Abstract: A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.

    Abstract translation: 公开了CMOS晶体管和制造CMOS晶体管的方法。 NMOS晶体管形成在半导体衬底的第一区域上。 PMOS晶体管形成在半导体衬底的第二区域上。 NMOS晶体管包括第一栅极导电层。 PMOS晶体管包括第二栅极导电层。 第一栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.0eV至约4.3eV的功函数。 第三栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.7eV至约5.0eV的功函数。

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