公开(公告)号：US07638365B2

公开(公告)日：2009-12-29

申请号：US11623279

申请日：2007-01-15

Applicant: Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

Inventor： Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L27/146 ,  H01L27/148 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

Abstract translation: 提供一种堆叠式芯片封装及其形成方法。 间隔件形成在上芯片的一侧。 在间隔件上形成导线以电连接上芯片和下芯片。 堆叠式芯片封装的可靠性得到改善，因为引线接合不用于电连接上下芯片。 此外，堆叠的芯片封装的整体尺寸可以减小，因为接合线环的高度对整个堆叠的芯片封装高度没有贡献。

公开(公告)号：US07626254B2

公开(公告)日：2009-12-01

申请号：US12121490

申请日：2008-05-15

Applicant: Min-Ho O ,  Jong-Ho Lee ,  Eun-Chul Ahn ,  Pyoung-Wan Kim

Inventor： Min-Ho O ,  Jong-Ho Lee ,  Eun-Chul Ahn ,  Pyoung-Wan Kim

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.

Abstract translation: 提供了使用芯片嵌入式插入器基板的半导体封装。 芯片嵌入式插入器基板包括：包括多个芯片焊盘的芯片; 具有安装在其上的芯片并且包括用于重新分配芯片焊盘的多个再分配焊盘的衬底; 用于将芯片焊盘连接到再分配焊盘的接合线; 保护层，其具有用于在掩埋所述芯片和所述基板的同时露出所述再分布焊盘的通孔; 以及通过通孔连接到再分配焊盘的通孔。 包括各种尺寸的芯片的半导体封装使用芯片嵌入式插入器基板来制造。

公开(公告)号：US07615830B2

公开(公告)日：2009-11-10

申请号：US11252514

申请日：2005-10-18

Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

IPC: H01L21/8238

CPC classification number: H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

公开(公告)号：US20090181278A1

公开(公告)日：2009-07-16

申请号：US12261962

申请日：2008-10-30

Applicant: Ji-Won Son ,  Hae-Weon Lee ,  Ki-Bum Kim ,  Chang-Woo Kwon ,  Jong-Ho Lee ,  Hae-Ryoung Kim

Inventor： Ji-Won Son ,  Hae-Weon Lee ,  Ki-Bum Kim ,  Chang-Woo Kwon ,  Jong-Ho Lee ,  Hae-Ryoung Kim

IPC: H01M8/10 ,  C23F1/00

CPC classification number: H01M8/1286 ,  C25D11/045 ,  C25D11/24 ,  C25D11/26 ,  C25D11/30 ,  C25D11/32 ,  C25D11/34 ,  H01M4/8878 ,  Y02P70/56

Abstract: A micro cell fuel cell using a nano porous structure according to a thin film process and an anodizing process as a template for implementing a porous structure of an electrode, its fabrication method, and a micro fuel cell stack using the same are disclosed. The micro-fuel cell includes a solid electrolyte and first and second electrodes separately formed on the electrolyte, wherein at least one of the first and second electrodes is supported by a template having a plurality of nano pores formed by depositing, anodizing and etching a thin film, and is a porous electrode with nano pores formed at positions corresponding to the entirety or a portion of the plurality of nano pores formed on the template. The micro-fuel cell can be fabricated based on the thin film process, and unit cells can be highly integrated to implement a micro-fuel cell system generating a high voltage and a high current.

Abstract translation: 公开了一种使用根据薄膜工艺的纳米多孔结构和用于实现电极的多孔结构，其制造方法和使用其的微型燃料电池堆的模板的阳极氧化工艺的微电池燃料电池。 微型燃料电池包括固体电解质和分别在电解质上形成的第一和第二电极，其中第一和第二电极中的至少一个被模板支撑，该模板具有通过沉积，阳极氧化和蚀刻薄的多个纳米孔 并且是在对应于形成在模板上的多个纳米孔的整体或一部分的位置处形成的具有纳米孔的多孔电极。 微型燃料电池可以基于薄膜工艺制造，并且单元电池可以被高度集成以实现产生高电压和高电流的微型燃料电池系统。

公开(公告)号：US20090157260A1

公开(公告)日：2009-06-18

申请号：US12326350

申请日：2008-12-02

Applicant: Jong Ho Lee

Inventor： Jong Ho Lee

IPC: B62D6/00

CPC classification number: B62D15/0285

Abstract: Disclosed herein is an automatic parking system for a vehicle. The automatic parking system employs a method of generating a parking trajectory in consideration of the operational performance of a steering motor connected to the steering wheel of a vehicle, thus guiding a vehicle through smooth parking and reducing an error between an ideal parking trajectory and an actual parking trajectory.

Abstract translation: 这里公开了一种用于车辆的自动停车系统。 考虑到连接到车辆的方向盘的转向电动机的操作性能，自动停车系统采用产生停车轨迹的方法，从而通过平稳停车引导车辆，并减少理想的停车轨迹与实际的停车轨迹之间的误差 停车轨迹。

公开(公告)号：US07547951B2

公开(公告)日：2009-06-16

申请号：US11396702

申请日：2006-04-04

Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Seok Kim ,  Min Joo Kim

Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Seok Kim ,  Min Joo Kim

IPC: H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823857

Abstract: A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

Abstract translation: 半导体器件可以包括具有第一区域和第二区域的半导体衬底。 可以在第一区域内形成含氮的有源区。 可以在引入氮的有源区上形成第一栅电极。 第一栅极电介质层可插入在引入氮的有源区和第一栅电极之间。 第一栅介质层可以包括第一介电层和第二介电层。 第二电介质层可以是含氮介电层。 第二栅极电极可以形成在第二区域上。 可以在第二区域和第二栅电极之间插入第二栅极电介质层。 第一栅极介电层可以具有与第二栅极介电层相同或基本相同的厚度，并且含氮介电层可以与引入氮的有源区接触。

公开(公告)号：US20090108358A1

公开(公告)日：2009-04-30

申请号：US11719923

申请日：2005-12-06

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7851 ,  H01L29/66621 ,  H01L29/7854

Abstract: The present invention relates to a nano-scale MOS device having a saddle structure. Particularly, the invention relates to a high-density, high-performance MOS device having a novel structure capable of improving the scaling-down characteristic and performance of the MOS device, in which a channel and gate structure is formed in the shape of a saddle. The inventive MOS device is mainly characterized in that a channel region is recessed, a gate insulating film and a gate electrode are formed on the surface and sides of the recessed channel, and the gate electrode is self-aligned with the recessed channel. Namely, in the disclosed MOS device, a portion of the insulating film around the recessed channel is selectively removed to expose the surface and sides of the recessed channel. According to the present invention, the scaling-down characteristic of the device is excellent and current drive capability is greatly increased since a channel through which an electric current can flow is formed on the surface and sides of the recessed channel. Also, the ability of the gate electrode to control the channel is enhanced. Accordingly, the invention can improve device characteristics.

Abstract translation: 本发明涉及具有鞍座结构的纳米级MOS器件。 特别地，本发明涉及一种具有能够提高MOS器件的放大特性和性能的新型结构的高密度高性能MOS器件，其中沟道和栅极结构形成为鞍形 。 本发明的MOS器件的主要特征在于沟槽区域凹陷，栅极绝缘膜和栅极电极形成在凹槽的表面和侧面上，并且栅电极与凹陷通道自对准。 也就是说，在所公开的MOS器件中，围绕凹槽的绝缘膜的一部分被选择性地去除以暴露凹槽的表面和侧面。 根据本发明，由于在凹陷通道的表面和侧面上形成有可以流过电流的通道，装置的缩小特性优异，电流驱动能力大大增加。 此外，增强了栅电极控制通道的能力。 因此，本发明可以提高装置特性。

公开(公告)号：US20090045513A1

公开(公告)日：2009-02-19

申请号：US12193561

申请日：2008-08-18

Applicant: Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

Inventor： Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Abstract translation: 一种包括半导体芯片的半导体芯片封装，所述半导体芯片包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US07399093B2

公开(公告)日：2008-07-15

申请号：US10664813

申请日：2003-09-17

Applicant: Taeg Ho Kang ,  Deog Jin Lee ,  Dong Kweon Shin ,  Ju Young Jeong ,  Jong Ho Lee ,  Yong Joo Lee

Inventor： Taeg Ho Kang ,  Deog Jin Lee ,  Dong Kweon Shin ,  Ju Young Jeong ,  Jong Ho Lee ,  Yong Joo Lee

IPC: G02B5/08 ,  G02B7/182

CPC classification number: H04N9/3141

Abstract: Disclosed is a reflection mirror of a projection television to prevent the frame of the projection television from being deformed and to fabricate the projection television with ease. The reflection mirror is fabricated by forming a plurality of ribs at a section of the frame and inserting a soft shield plate between the ribs.

Abstract translation: 公开了一种投影电视机的反射镜，以防止投影电视机的框架变形并且容易地制造投影电视机。 通过在框架的一部分处形成多个肋并在软肋之间插入软屏蔽板来制造反射镜。

公开(公告)号：US20080109725A1

公开(公告)日：2008-05-08

申请号：US11957693

申请日：2007-12-17

Applicant: Jong-ho LEE ,  Kwang-kee LEE ,  Sung-wook BYUN ,  Glenn ADAMS ,  Un-gyo JUNG

Inventor： Jong-ho LEE ,  Kwang-kee LEE ,  Sung-wook BYUN ,  Glenn ADAMS ,  Un-gyo JUNG

IPC: G06F3/048

CPC classification number: H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/8715

Abstract: An apparatus for providing multiple screens and a method of dynamically configuring multiple screens are provided. The apparatus includes a digital signal processing module which receives at least one of video information, audio information, and data information and restores a plurality of services based on the at least one of the video information, the audio information and the data information; a service processing module which generates a display screen and a plurality of logical screens for displaying the restored services; and an output module which maps the plurality of logical screens generated by the service processing module to different locations on the display screen, wherein each of the logical screens includes an instance providing graphics, the instance includes a plurality of frames on which an application is executed, and each of the frames has arrangement attribute information indicating an arrangement order.

Abstract translation: 提供了一种用于提供多个屏幕的装置和一种动态配置多个屏幕的方法。 该装置包括数字信号处理模块，其接收视频信息，音频信息和数据信息中的至少一个，并且基于视频信息，音频信息和数据信息中的至少一个来恢复多个服务; 服务处理模块，其生成显示屏幕和用于显示恢复的服务的多个逻辑屏幕; 以及输出模块，其将由服务处理模块生成的多个逻辑画面映射到显示屏幕上的不同位置，其中每个逻辑画面包括提供图形的实例，该实例包括执行应用的多个帧 ，并且每个帧具有指示排列顺序的排列属性信息。