公开(公告)号：US20100046304A1

公开(公告)日：2010-02-25

申请号：US12539829

申请日：2009-08-12

Applicant: Jae-hun JEONG ,  Soon-moon JUNG ,  Han-soo KIM ,  Jae-hoon JANG

Inventor： Jae-hun JEONG ,  Soon-moon JUNG ,  Han-soo KIM ,  Jae-hoon JANG

IPC: G11C16/16 ,  G11C16/04 ,  G11C11/34

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.

Abstract translation: 提供了一种非易失性存储器件，包括第一和第二垂直堆叠的半导体衬底，在第一和第二半导体衬底上形成为一行的多个非易失性存储单元晶体管，以及连接到第一和第二半导体衬底的栅极的多条字线 多个非易失性存储单元晶体管。 多个非易失性存储单元晶体管被分组成两个或更多个存储单元块，使得第一电压被施加到第一半导体衬底，该第一半导体衬底包括要擦除的第一存储单元块，以及（1）第二电压较小 比不包括第一存储单元块的第二半导体衬底施加大于0V的第一电压，或者（2）不包括第一存储单元块的第二半导体衬底被电浮动。

公开(公告)号：US20100046294A1

公开(公告)日：2010-02-25

申请号：US12486924

申请日：2009-06-18

Applicant: Jae-hun JEONG ,  Soon-moon JUNG ,  Han-soo KIM ,  Jae-hoon JANG

Inventor： Jae-hun JEONG ,  Soon-moon JUNG ,  Han-soo KIM ,  Jae-hoon JANG

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages.

Abstract translation: 非易失性存储器件包括分别连接到第一串存储单元晶体管的栅极的第一和第二串存储单元晶体管，相关的第一和第二字线，其中相应的第一和第二字线被连接以共同接收偏置电压。 非易失性存储器件还包括连接到第一和第二串的虚拟单元晶体管，以及被配置为接收不同偏置电压的第一和第二虚拟字线。

公开(公告)号：US20100035386A1

公开(公告)日：2010-02-11

申请号：US12588240

申请日：2009-10-08

Applicant: Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

Inventor： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

IPC: H01L21/768

CPC classification number: H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

Abstract translation: 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

公开(公告)号：US20090253257A1

公开(公告)日：2009-10-08

申请号：US12478538

申请日：2009-06-04

Applicant: Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

Inventor： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC: H01L21/8246 ,  H01L21/4763 ,  H01L21/3205

CPC classification number: H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

Abstract translation: 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US20090097214A1

公开(公告)日：2009-04-16

申请号：US12152442

申请日：2008-05-14

Applicant: Jin-woo Lee ,  Jae-hoon Jang

Inventor： Jin-woo Lee ,  Jae-hoon Jang

IPC: H05K5/00 ,  H05K3/02

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L23/5389 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H05K1/189 ,  H05K3/4069 ,  H05K3/422 ,  H05K3/4614 ,  H05K2201/09036 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: Provided is a method of manufacturing a device-embedded circuit board. The method includes: preparing a first substrate with a first pattern portion comprising a conductive material; coupling, for example, an electronic chip to the first substrate; preparing a second substrate with a first through hole corresponding to a part of the first pattern portion, a housing portion for housing the electronic chip, and a first connection portion comprising a conductive material formed in the first through hole; preparing a third substrate with a second through hole corresponding to the first through hole and a second connection portion comprising a conductive material formed in the second through hole; aligning and coupling the first, second and third substrates so that the first pattern portion, the first connection portion and the second connection portion are electrically connected.

Abstract translation: 提供了一种制造器件嵌入式电路板的方法。 该方法包括：制备具有包括导电材料的第一图案部分的第一基板; 将例如电子芯片耦合到第一基板; 制备具有对应于第一图形部分的一部分的第一通孔的第二基板，用于容纳电子芯片的壳体部分和包括形成在第一通孔中的导电材料的第一连接部分; 制备具有对应于第一通孔的第二通孔的第三基板和包括形成在第二通孔中的导电材料的第二连接部分; 对准和耦合第一，第二和第三基板，使得第一图案部分，第一连接部分和第二连接部分电连接。

公开(公告)号：US20080193024A1

公开(公告)日：2008-08-14

申请号：US12031270

申请日：2008-02-14

Applicant: Suh-Ho Lee ,  Joo-Kwang Kim ,  Won-Seok Heo ,  Jae-Hoon Jang

Inventor： Suh-Ho Lee ,  Joo-Kwang Kim ,  Won-Seok Heo ,  Jae-Hoon Jang

IPC: G06K9/40

CPC classification number: H04N19/86 ,  H04N19/423

Abstract: An apparatus deblock filters in a digital moving picture processing system with a macro block having a predetermined number of pixel blocks. An external memory controller reads a current sub-block of a current macro block from entire image data stored in an external memory, and delivers image data of an internal pixel block constituting the current sub-block and an external pixel block to a filter-dedicated memory. The filter-dedicated memory stores the delivered image data. A filtering operator performs horizontal filtering on the current sub-block using the stored image data according to a predetermined order, and performs vertical filtering on the current sub-block according to a predetermined order when the horizontal filtering is completed. The external pixel block includes pixel blocks adjacent to a top and a left side among pixel blocks adjacent to the internal pixel block.

Abstract translation: 具有具有预定数量的像素块的宏块的数字运动图像处理系统中的装置去块滤波器。 外部存储器控制器从存储在外部存储器中的整个图像数据读取当前宏块的当前子块，并将构成当前子块的内部像素块和外部像素块的图像数据传送到过滤器专用 记忆。 过滤器专用存储器存储所递送的图像数据。 过滤运算符根据预定顺序对存储的图像数据对当前子块执行水平滤波，并且当水平滤波完成时，根据预定顺序对当前子块进行垂直滤波。 外部像素块包括与内部像素块相邻的像素块中的与顶部和左侧相邻的像素块。

公开(公告)号：US20080111121A1

公开(公告)日：2008-05-15

申请号：US11855952

申请日：2007-09-14

Applicant: Jae-Hoon JANG ,  Ki-Nam KIM ,  Soon-Moon JUNG

Inventor： Jae-Hoon JANG ,  Ki-Nam KIM ,  Soon-Moon JUNG

IPC: H01L47/00

CPC classification number: G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L45/1683 ,  Y10S257/91

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract translation: 公开了一种相变存储器件及其制造方法。 相变存储器件包括具有第一导电类型和侧壁的第一导体图案。 第二导体图案连接到第一导体图案的侧壁以形成二极管。 相变层电连接到第二导体图案，顶电极连接到相变层。

公开(公告)号：US20060097319A1

公开(公告)日：2006-05-11

申请号：US11197836

申请日：2005-08-05

Applicant: Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

Inventor： Jong-Hyuk Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Sung-Jin Kim ,  Jae-Joo Shim

IPC: H01L27/01

CPC classification number: H01L21/8221 ,  H01L21/28525 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L29/785

Abstract: Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.

Abstract translation: 提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。 所述方法包括在单晶半导体层上形成层间绝缘层。 形成单晶半导体插塞以穿透层间绝缘层。 使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。 结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。 也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。 单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。 通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

公开(公告)号：US20050179061A1

公开(公告)日：2005-08-18

申请号：US11033432

申请日：2005-01-11

Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L29/41 ,  H01L29/786 ,  H01L27/10

CPC classification number: H01L27/1214 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

Abstract: Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

Abstract translation: 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

公开(公告)号：US10199116B2

公开(公告)日：2019-02-05

申请号：US15664303

申请日：2017-07-31

Applicant: Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.