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    TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY
    32.
    发明申请
    TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY 有权
    从图书馆创建的半导体产品的测试估计

    公开(公告)号：US20080189664A1

    公开(公告)日：2008-08-07

    申请号：US12062586

    申请日：2008-04-04

    Applicant: Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    Inventor： Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.

    Abstract translation: 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

    REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTERGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME
    34.
    发明申请
    REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTERGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME 有权
    用于集成电路的冗余微环结构物理设计过程及其形成方法

    公开(公告)号：US20080150149A1

    公开(公告)日：2008-06-26

    申请号：US12045374

    申请日：2008-03-10

    Applicant: Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    Inventor： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    IPC: H01L23/52 ,  G06F17/50

    CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

    Abstract translation: 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和与第二线的第一距离的第四线 第二层线路。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。 第三通过在第四线的第二位置连接第三和第四导线。 第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

    Content based yield prediction of VLSI designs
    35.
    发明授权
    Content based yield prediction of VLSI designs 有权
    基于内容的VLSI设计的产量预测

    公开(公告)号：US07389480B2

    公开(公告)日：2008-06-17

    申请号：US10908342

    申请日：2005-05-09

    Applicant: Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    Inventor： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

    Abstract translation: 一种用于预测VLSI设计产量的系统，方法和程序产品。 提供了一种方法，包括以下步骤：通过类型识别和分组集成电路设计中包含的子电路; 计算集成电路设计中区域的关键面积值; 以及基于用于计算临界面积值的区域的类型将不同的屈服模型应用于临界区域值，其中每个产量模型依赖于类型。

    Use of redundant routes to increase the yield and reliability of a VLSI layout
    36.
    发明授权
    Use of redundant routes to increase the yield and reliability of a VLSI layout 有权
    使用冗余路由来提高VLSI布局的收益和可靠性

    公开(公告)号：US07308669B2

    公开(公告)日：2007-12-11

    申请号：US10908593

    申请日：2005-05-18

    Applicant: Markus T. Buehler ,  John M. Cohn ,  David J. Hathaway ,  Jason D. Hibbeler ,  Juergen Koehl

    Inventor： Markus T. Buehler ,  John M. Cohn ,  David J. Hathaway ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5068

    Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

    Abstract translation: 公开了一种将冗余路径插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用替代 路线。 第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。 更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。 如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

    Use of a layout-optimization tool to increase the yield and reliability of VLSI designs
    38.
    发明授权
    Use of a layout-optimization tool to increase the yield and reliability of VLSI designs 失效
    使用布局优化工具来提高VLSI设计的产出和可靠性

    公开(公告)号：US06941528B2

    公开(公告)日：2005-09-06

    申请号：US10604962

    申请日：2003-08-28

    Applicant: Robert J. Allen ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    Inventor： Robert J. Allen ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    IPC: G06F9/45 ,  G06F17/50

    CPC classification number: G06F17/5068

    Abstract: The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. The invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via.

    Abstract translation: 本发明提供了一种用于优化集成电路设计中的冗余通孔的布置的方法和结构。 本发明首先通过确定哪些通孔没有冗余通孔来定位目标通孔。 然后，本发明在目标通孔上或附近绘制标记物形状。 标记形状仅在每个目标通孔的水平或垂直方向绘制。 本发明同时将第一方向上的所有标记形状扩展到预定长度，或者直到标记形状达到接地规则的极限。 在扩展期间，不同的标记形状将被扩展到不同的长度。 本发明确定哪些标记形状被充分扩展以形成有效的冗余通路以产生第一组潜在的冗余通孔，并且本发明消除了不能充分扩展以形成有效的冗余通路的标记形状。

    Image sensor pixel structure employing a shared floating diffusion
    40.
    发明授权
    Image sensor pixel structure employing a shared floating diffusion 有权
    采用共享浮动扩散的图像传感器像素结构

    公开(公告)号：US08405751B2

    公开(公告)日：2013-03-26

    申请号：US12534427

    申请日：2009-08-03

    Applicant: Jason D. Hibbeler ,  Daniel N. Maynard ,  Kevin N. Ogg ,  Richard J. Rassel

    Inventor： Jason D. Hibbeler ,  Daniel N. Maynard ,  Kevin N. Ogg ,  Richard J. Rassel

    IPC: H04N5/335

    CPC classification number: H01L27/14609 ,  H01L27/14641 ,  H01L27/14643 ,  H04N5/37457

    Abstract: A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.

    Abstract translation: 图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。 四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。 四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。 公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

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