公开(公告)号：US07696507B2

公开(公告)日：2010-04-13

申请号：US11907844

申请日：2007-10-18

Applicant: Yoon-ho Khang ,  Ki-joon Kim ,  Dong-seok Suh

Inventor： Yoon-ho Khang ,  Ki-joon Kim ,  Dong-seok Suh

IPC: H01L47/00

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may include a switching device and the storage node. The switching device may be connected to the bottom electrode contact layer. A method of manufacturing the storage node may include forming a via hole in an insulating interlayer, at least partially filling the via hole to form a bottom electrode contact layer, protruding the bottom electrode contact layer from the via hole, and forming a phase change layer that covers the bottom electrode contact layer. A method of manufacturing a phase change memory device may include forming the switching device on a substrate and manufacturing the storage node.

Abstract translation: 存储节点可以包括底部电极接触层，连接到底部电极接触层的相变层和连接到相变层的顶部电极层。 底部电极接触层可以向相变层突出。 相变存储器件可以包括切换装置和存储节点。 开关器件可以连接到底部电极接触层。 制造存储节点的方法可以包括在绝缘中间层中形成通孔，至少部分地填充通孔以形成底电极接触层，从底孔电极接触层从通孔突出，并形成相变层 覆盖底部电极接触层。 相变存储器件的制造方法可以包括在基板上形成开关器件并制造存储节点。

公开(公告)号：US07592993B2

公开(公告)日：2009-09-22

申请号：US11255834

申请日：2005-10-21

Applicant: Ki-Joon Kim

Inventor： Ki-Joon Kim

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0291 ,  G09G2310/08

Abstract: There is provided a source driver capable of controlling the timing of source line driving signals in a liquid crystal display device. The source driver includes a plurality of output circuits, each output circuit including an output buffer and a switch. The output buffer amplifies an analog image signal, and the switch outputs the amplified analog image signal as a source line driving signal in response to a control signal. The source driver further comprises a control circuit for generating the control signal, the control circuit comprising: a delay circuit delaying a switch signal and generating a delayed switch signal; and a multiplexer selecting one of the switch signal and the delayed switch signal in response to a selection signal and outputting the selected signal as the control signal.

Abstract translation: 提供了能够控制液晶显示装置中的源极线驱动信号的定时的源极驱动器。 源极驱动器包括多个输出电路，每个输出电路包括输出缓冲器和开关。 输出缓冲器放大模拟图像信号，并且开关响应于控制信号而输出放大的模拟图像信号作为源极线驱动信号。 源极驱动器还包括用于产生控制信号的控制电路，所述控制电路包括：延迟电路，延迟开关信号并产生延迟的开关信号; 以及多路复用器，响应于选择信号选择开关信号和延迟开关信号之一，并输出所选择的信号作为控制信号。

公开(公告)号：US20090184727A1

公开(公告)日：2009-07-23

申请号：US12223967

申请日：2007-02-13

Applicant: Ki-Joon Kim ,  Yong-Hwi Jo ,  Dong Yeul Choi

Inventor： Ki-Joon Kim ,  Yong-Hwi Jo ,  Dong Yeul Choi

IPC: G01R31/02 ,  H05K3/10

CPC classification number: G01R1/07378 ,  G01R31/2889 ,  Y10T29/49155

Abstract: Provided is a probe card of a semiconductor testing apparatus, including a printed circuit board to which an electrical signal is applied from external, a space transformer having a plurality of probes directly contacting with a test object, and interconnectors connecting the printed circuit board to the probes of the space transformer. The space transformer includes substrate pieces which the probes are installed on one sides of, and a combination member joining and unifying the substrate pieces together so as to form a large-area substrate with the substrate pieces on the same plane. This probe card is advantageous to improving flatness even with a large area, as well as testing semiconductor chips formed on a wafer in a lump.

Abstract translation: 提供一种半导体测试装置的探针卡，包括从外部施加电信号的印刷电路板，具有与测试对象直接接触的多个探针的空间变压器以及将印刷电路板连接到测试对象的互连器 空间变压器探头。 空间变压器包括探针安装在其一侧的基片和将基片拼接在一起的组合件，以便形成具有基片的同一平面上的大面积基片。 该探针卡有利于即使在大面积上提高平坦度，也有利于测试在一个晶片上形成的半导体芯片。

公开(公告)号：US20090128180A1

公开(公告)日：2009-05-21

申请号：US11990275

申请日：2006-08-02

Applicant: Ki-Joon Kim ,  Yong-Hwi Jo

Inventor： Ki-Joon Kim ,  Yong-Hwi Jo

IPC: G01R1/067 ,  G01R31/02 ,  C25F3/12

CPC classification number: G01R1/06727 ,  G01R3/00 ,  Y10T29/49004

Abstract: Disclosed is a cantilever-type probe and methods of fabricating the same. The probe is comprised of a cantilever being longer lengthwise relative to the directions of width and height, and a tip extending from the bottom of the cantilever and formed at an end of the cantilever. A section of the tip parallel to the bottom of the cantilever is rectangular, having four sides slant to the lengthwise direction of the cantilever.

Abstract translation: 公开了一种悬臂式探针及其制造方法。 探头由相对于宽度和高度方向的纵向长度的悬臂组成，以及从悬臂的底部延伸并形成在悬臂的端部处的尖端。 平行于悬臂底部的尖端的一部分是矩形的，具有沿着悬臂的长度方向倾斜的四个边。

公开(公告)号：US20080173860A1

公开(公告)日：2008-07-24

申请号：US12007014

申请日：2008-01-04

Applicant: Woong-chul Shin ,  Ki-joon Kim ,  Ji-hyun Hur ,  Hyo-sug Lee

Inventor： Woong-chul Shin ,  Ki-joon Kim ,  Ji-hyun Hur ,  Hyo-sug Lee

IPC: H01L45/00

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683

Abstract: Provided are a phase change memory device and a method of fabricating the same. The phase change memory device including a phase change layer in a storage node thereof includes: a bottom electrode; a bottom electrode contact layer formed of a phase change material disposed on the bottom electrode; a first phase change layer having a smaller width than the bottom electrode contact layer, disposed on the bottom electrode contact layer; a second phase change layer having a larger width than the first phase change layer, disposed on the first phase change layer; and a upper electrode disposed on the second phase change layer.

Abstract translation: 提供一种相变存储器件及其制造方法。 包括其存储节点中的相变层的相变存储器件包括：底部电极; 由设置在所述底部电极上的相变材料形成的底部电极接触层; 设置在底部电极接触层上的具有比底部电极接触层更小的宽度的第一相变层; 设置在所述第一相变层上的具有比所述第一相变层宽的宽度的第二相变层; 以及设置在第二相变层上的上电极。

公开(公告)号：US4918029A

公开(公告)日：1990-04-17

申请号：US157981

申请日：1988-02-19

Applicant: Ki-Joon Kim

Inventor： Ki-Joon Kim

IPC: H01L21/208 ,  C30B19/02 ,  C30B19/06 ,  C30B19/08

CPC classification number: C30B19/02 ,  C30B19/063 ,  C30B19/08 ,  C30B29/40 ,  Y10S148/101

Abstract: A device and method for liquid-phase thin film epitaxial growth are disclosed wherein yield and quality of semiconductors in the fabrication sequences are improved. The device comprises an electric furnace which is disposed outside a quartz tube, a plurality of boats which are disposed within the quartz tube in accordance with a sort of melting liquids and a plurality of auxiliary heating devices are disposed around the boats with a power source independent from the electric furnace. According to this fabrication sequence, after heating the inner part of the quartz tube up to a first temperature level by supplying the power source to the electric furnace, the melting liquids are firstly melted down enough by means of selectively heating the auxiliary heating devices up to a second temperature level higher than the first temperature level, the substrates are then moved to be in contact with the melting liquids and an epitaxial growth layer is consequently formed through selectively reducing the temperature of the auxiliary heating devices to other levels different from the first and second level.

Abstract translation: 公开了用于液相薄膜外延生长的装置和方法，其中制造顺序中的半导体的产率和质量得到改善。 该装置包括设置在石英管外部的电炉，根据一种熔化液体和多个辅助加热装置设置在石英管内的多个船只设置在船舶周围，电源独立 从电炉。 根据该制造顺序，通过向电炉供给电源，将石英管的内部部分加热到第一温度水平之后，熔融液首先通过选择性地加热辅助加热装置而熔化到最高 第二温度水平高于第一温度水平，然后基板移动以与熔化液体接触，因此通过选择性地将辅助加热装置的温度降低到与第一和第二温度不同的其他水平，形成外延生长层 二级

公开(公告)号：US09356071B2

公开(公告)日：2016-05-31

申请号：US14804310

申请日：2015-07-20

Applicant: Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

Inventor： Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L21/311 ,  H01L29/82 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

公开(公告)号：US20150325625A1

公开(公告)日：2015-11-12

申请号：US14804310

申请日：2015-07-20

Applicant: Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

Inventor： Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

Abstract translation: 在基板上形成绝缘层。 在绝缘层上形成第一掩模。 第一掩模包括沿第二方向布置的多个线图案。 多个线图案沿着基本上垂直于第二方向的第一方向延伸。 在绝缘层和第一掩模上形成第二掩模。 第二掩模包括部分地暴露多个线图案的开口。 开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。 使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。 多个第一沟槽和第二沟槽以交错图案布置。

公开(公告)号：US20140377950A1

公开(公告)日：2014-12-25

申请号：US14285969

申请日：2014-05-23

Applicant: Yong-Jun KIM ,  Kil-Ho LEE ,  Ki-Joon KIM ,  Myoung-Su SON

Inventor： Yong-Jun KIM ,  Kil-Ho LEE ,  Ki-Joon KIM ,  Myoung-Su SON

IPC: H01L21/768

CPC classification number: H01L21/76807

Abstract: A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.

Abstract translation: 一种制造半导体器件的方法，包括形成模制层; 在成型层上形成镶嵌掩模层和掩模层; 通过蚀刻掩模层形成掩模层图案; 通过部分蚀刻镶嵌掩模层形成镶嵌图案; 在掩模层图案上形成镶嵌掩模层以埋藏镶嵌图案; 通过蚀刻镶嵌掩模层和掩模层图案形成部分地与镶嵌图案重叠的镶嵌图案; 通过去除由镶嵌图案暴露的掩模层图案的一部分来连接镶嵌图案和镶嵌图案; 在镶嵌掩模层上形成镶嵌掩模层，以埋藏镶嵌图案; 以及通过使用掩模层图案的剩余部分蚀刻镶嵌掩模层和模制层，在镶嵌图案之下形成沟槽。

公开(公告)号：US08917266B2

公开(公告)日：2014-12-23

申请号：US13439388

申请日：2012-04-04

Applicant: Yong-Yun Park ,  Jong-Seon Kim ,  Ki-Joon Kim ,  Min-Hwa Jang

Inventor： Yong-Yun Park ,  Jong-Seon Kim ,  Ki-Joon Kim ,  Min-Hwa Jang

IPC: G09G5/10 ,  G09G3/20 ,  G09G3/36 ,  G09G5/36

CPC classification number: G09G3/2096 ,  G09G3/3688 ,  G09G5/363 ,  G09G2230/00 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/0294 ,  G09G2320/103 ,  G09G2330/04 ,  G09G2340/02 ,  G09G2340/16 ,  G09G2360/18

Abstract: A timing controller that includes a noise detection circuit and a setting control unit. The noise detection circuit includes a detection unit and a reset signal generating unit. The detection unit outputs a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal. The reset signal generating unit outputs a reset signal having a second logic level based on the detection signal. The setting control unit stores setting data and initializes the setting data in response to the reset signal having the first logic level, and the setting data are used to process red, green and blue (RGB) image data.

Abstract translation: 包括噪声检测电路和设定控制单元的定时控制器。 噪声检测电路包括检测单元和复位信号生成单元。 检测单元基于多个参考数据中的至少一个输出具有与时钟信号异步的第一逻辑电平的检测信号。 复位信号生成单元基于检测信号输出具有第二逻辑电平的复位信号。 设置控制单元存储设置数据并响应于具有第一逻辑电平的复位信号来初始化设置数据，并且设置数据用于处理红，绿和蓝（RGB）图像数据。