公开(公告)号：US20150179271A1

公开(公告)日：2015-06-25

申请号：US14501352

申请日：2014-09-30

申请人： SANG-WAN NAM ,  KANG-BIN LEE ,  KIHWAN CHOI

发明人： SANG-WAN NAM ,  KANG-BIN LEE ,  KIHWAN CHOI

IPC分类号： G11C16/16 ,  G11C11/16 ,  G11C13/00

CPC分类号： G11C16/16 ,  G11C11/16 ,  G11C16/0483

摘要： A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block.

摘要翻译： 提供了一种用于擦除非易失性存储器件的方法，包括沿垂直于衬底的方向形成的多个存储块，每个存储块具有连接到位线的多个串。 该方法包括使用电源电压选择要擦除的存储器块; 使用负电压取消选择存储块以外的剩余存储块; 设置偏置条件以减少未选择的存储器块的漏电流; 以及对所选存储块执行擦除操作。

公开(公告)号：US09053978B2

公开(公告)日：2015-06-09

申请号：US13478569

申请日：2012-05-23

申请人： Sang-Wan Nam

发明人： Sang-Wan Nam

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/16 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage.

摘要翻译： 非易失性存储器件的擦除系统和方法包括向非易失性存储器的多个存储单元提供擦除电压，对多个存储器单元的字线执行读取电压读取操作，并执行擦除验证操作 具有擦除验证电压至所述多个存储单元中的至少一个字线，所述擦除验证电压低于读取电压。

公开(公告)号：US20150009760A1

公开(公告)日：2015-01-08

申请号：US14153164

申请日：2014-01-13

申请人： SANG-WAN NAM ,  WON-TAECK JUNG

发明人： SANG-WAN NAM ,  WON-TAECK JUNG

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427

摘要： A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

摘要翻译： 非易失性存储器件执行包括第一和第二间隔的读取操作。 在第一间隔期间，器件分别对串联选择线和连接到串选择晶体管和接地选择晶体管的选择线施加导通电压。 在第二间隔期间，器件对未选择的串选择线和未选择的接地选择线施加关断电压，同时继续对所选择的串选择线和选择的接地选择线施加导通电压。 在第一和第二间隔中，设备将第一读取电压施加到连接到要由读取操作读取的存储器单元的选定字线，并将第二读取电压施加到连接到不被读取的存储器单元读取的未选字线 读操作。

公开(公告)号：US08837228B2

公开(公告)日：2014-09-16

申请号：US13597534

申请日：2012-08-29

申请人： Sang-Wan Nam ,  Won-Teack Jung ,  Junghoon Park

发明人： Sang-Wan Nam ,  Won-Teack Jung ,  Junghoon Park

IPC分类号： G11C16/16 ,  G11C16/04 ,  H01L27/115 ,  G11C16/34 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

摘要： An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.

摘要翻译： 非易失性存储器的擦除方法包括向衬底提供擦除电压，将选择字线电压提供给与非易失性存储器的存储块内的选定子块相连的字线，将非选择字线电压提供给 在从提供擦除电压的时间点起的第一延迟时间期间，与存储器块内的未选择子块相连的字线，然后浮动与未选择子块相连的字线。

公开(公告)号：US08472247B2

公开(公告)日：2013-06-25

申请号：US13157344

申请日：2011-06-10

申请人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

发明人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418

摘要： A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.

摘要翻译： 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。

公开(公告)号：US20130088921A1

公开(公告)日：2013-04-11

申请号：US13587955

申请日：2012-08-17

申请人： SANG-WAN NAM ,  KANG-BIN LEE ,  JUNGHOON PARK

发明人： SANG-WAN NAM ,  KANG-BIN LEE ,  JUNGHOON PARK

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

摘要： An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.

公开(公告)号：US20130007353A1

公开(公告)日：2013-01-03

申请号：US13607038

申请日：2012-09-07

申请人： Sunil SHIM ,  Jinman HAN ,  Sang-Wan NAM ,  Won-Taeck JUNG

发明人： Sunil SHIM ,  Jinman HAN ,  Sang-Wan NAM ,  Won-Taeck JUNG

IPC分类号： G06F12/02

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/349 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block.

公开(公告)号：US20120201080A1

公开(公告)日：2012-08-09

申请号：US13368769

申请日：2012-02-08

申请人： Kyung-Hwa KANG ,  Sang-Wan NAM ,  Donghyuk CHAE ,  ChiWeon YOON

发明人： Kyung-Hwa KANG ,  Sang-Wan NAM ,  Donghyuk CHAE ,  ChiWeon YOON

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/08

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

摘要翻译： 非易失性存储器件包括具有连接在衬底和多个位线之间并由选择线选择的多个单元串的存储单元阵列，以及配置成在至少两个方向上驱动选择线的选通电路。

公开(公告)号：US20120063235A1

公开(公告)日：2012-03-15

申请号：US13229107

申请日：2011-09-09

申请人： Chi Weon Yoon ,  Sang-Wan Nam ,  Dong Hyuk Chae

发明人： Chi Weon Yoon ,  Sang-Wan Nam ,  Dong Hyuk Chae

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3418

摘要： A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.

摘要翻译： 三维（3D）非易失性存储器包括存储单元阵列和合并驱动器，其被配置为将相同电平的合并电压施加到存储单元阵列中的公共源线和体。

公开(公告)号：US20090251961A1

公开(公告)日：2009-10-08

申请号：US12401784

申请日：2009-03-11

申请人： Sang-Wan NAM ,  Dae-Han KIM

发明人： Sang-Wan NAM ,  Dae-Han KIM

IPC分类号： G11C16/06 ,  G11C7/00 ,  G05F1/10

CPC分类号： G11C16/30 ,  G11C5/145

摘要： Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage.

摘要翻译： 公开了一种闪速存储器件，其包括存储器芯，高电压产生电路和参考电压产生电路。 高电压产生电路被配置为产生要提供给存储器芯的高电压。 参考电压产生电路被配置为产生要提供给高电压发生电路的至少一个参考电压。 参考电压产生电路包括被配置为响应于电源电压产生第一参考电压的第一参考电压发生器和被配置为响应于第一参考电压产生第二参考电压的第二参考电压发生器。 提供给高电压产生电路的至少一个参考电压包括第二参考电压。