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    Methods of manufacturing semiconductor devices
    31.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08815672B2

    公开(公告)日：2014-08-26

    申请号：US13223783

    申请日：2011-09-01

    Applicant: Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

    Inventor： Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

    IPC: H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7843

    Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

    Abstract translation: 一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一 以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成 第一外延层，以填充第一沟槽。

    Circuit in a semiconductor memory for programming operation modes of the memory
    33.
    发明授权
    Circuit in a semiconductor memory for programming operation modes of the memory 失效
    用于存储器的编程操作模式的半导体存储器中的电路

    公开(公告)号：US5838990A

    公开(公告)日：1998-11-17

    申请号：US905562

    申请日：1997-08-04

    Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F9/00 ,  G06F13/16

    CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Synchronous dram having a plurality of latency modes
    34.
    发明授权
    Synchronous dram having a plurality of latency modes 失效
    具有多个等待时间模式的同步电话

    公开(公告)号：US5835956A

    公开(公告)日：1998-11-10

    申请号：US822148

    申请日：1997-03-17

    Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F13/16

    CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Circuits for block redundancy repair of integrated circuit memory devices
    35.
    发明授权
    Circuits for block redundancy repair of integrated circuit memory devices 失效
    集成电路存储器件的块冗余修复电路

    公开(公告)号：US5742547A

    公开(公告)日：1998-04-21

    申请号：US701634

    申请日：1996-08-22

    Applicant: Seung-hun Lee

    Inventor： Seung-hun Lee

    IPC: G11C11/401 ,  G06T1/60 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC classification number: G11C29/81 ,  G06T1/60

    Abstract: A memory cell array includes a plurality of memory blocks, each of which includes normal memory cells and spare memory cells, arranged in arrays having rows and columns. A row or column of spare memory cells in one of the memory cell blocks is substituted for a defective row or column of normal memory cells in the one of the memory blocks, without substituting a row or column of spare memory cells in remaining ones of the memory cell blocks for a row or column of normal memory cells in the remaining ones of the memory blocks. Stated differently, a predetermined row or column of spare memory cells in a first one of the memory blocks is substituted for a first defective row or column of normal memory cells in the first one of the memory blocks, and the predetermined row or column of spare memory cells in a second one of the memory blocks is also substituted for a second defective row or column of normal memory cells in a second one of the memory blocks. Thus, a given row or column of spare memory cells can be used to substitute for different rows or columns of memory cells in each memory block. The number of spare memory cells which is required is thereby reduced.

    Abstract translation: 存储单元阵列包括多个存储块，每个存储块包括普通存储器单元和备用存储器单元，排列成具有行和列的阵列。 其中一个存储单元块中的备用存储器单元的一行或一列代替存储器块中的一个存储器块中的一个有缺陷的行或列的常规存储器单元，而不用代替剩余存储器单元中的剩余存储器单元的行或列 存储单元块，用于存储块中剩余存储单元中的正常存储器单元的行或列。 换句话说，第一个存储块中的预定行或列备用存储器单元被替换为第一个存储块中的第一个缺陷行或一列常规存储器单元，并且预定的行或列的备用 第二个存储块中的存储单元也被替换为第二个存储块中的第二个缺陷行或一列常规存储单元。 因此，给定的行或列的备用存储单元可以用于替代每个存储块中的不同行或列的存储单元。 从而减少了所需的备用存储单元的数量。

    Semiconductor memory
    36.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5703828A

    公开(公告)日：1997-12-30

    申请号：US580622

    申请日：1995-12-29

    Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

    CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Integrated circuit memory devices including banks of memory blocks
    37.
    发明授权
    Integrated circuit memory devices including banks of memory blocks 失效
    集成电路存储器件包括存储器块组

    公开(公告)号：US5701271A

    公开(公告)日：1997-12-23

    申请号：US703203

    申请日：1996-08-26

    Applicant: Seung-hun Lee

    Inventor： Seung-hun Lee

    IPC: G11C11/41 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C13/00

    CPC classification number: G11C7/10

    Abstract: An integrated circuit memory device includes a plurality of memory banks. Each of the memory banks includes a first array of at least four memory blocks and a second array of at least four memory blocks wherein each of the memory blocks includes at least two bit lines. Each of the memory blocks from the second array is paired with a respective memory block from the first array and the memory blocks are activated as pairs with at least one pair being activated during a data access operation. Four data lines are provided adjacent the first and second arrays of memory blocks. A plurality of input/output lines directly connects two of the bit lines from each of the memory blocks with two of the input/output lines so that for any pair of the memory blocks, two bit lines from each memory block of the pair are connected to separate data lines.

    Abstract translation: 集成电路存储器件包括多个存储体。 每个存储体包括至少四个存储器块的第一阵列和至少四个存储器块的第二阵列，其中每个存储器块包括至少两个位线。 来自第二阵列的每个存储器块与来自第一阵列的相应存储器块配对，并且存储块被激活成对，在数据访问操作期间至少有一对被激活。 在第一和第二存储块阵列附近提供四条数据线。 多个输入/输出线直接连接来自每个存储器块的两个位线与两个输入/输出线，使得对于任何一对存储器块，来自该对的每个存储器块的两个位线被连接 分隔数据线。

    COMPOSITION COMPRISING DENDROPANAX MORBIFERA EXTRACT
    38.
    发明申请
    COMPOSITION COMPRISING DENDROPANAX MORBIFERA EXTRACT 审中-公开
    包含DENDROPANAX MORBIFERA提取物的组合物

    公开(公告)号：US20170049832A1

    公开(公告)日：2017-02-23

    申请号：US15221527

    申请日：2016-07-27

    Applicant: Seung Hun LEE

    Inventor： Seung Hun LEE

    IPC: A61K36/25 ,  A61Q17/04 ,  C11B9/02 ,  A61K8/97

    CPC classification number: A61K36/25 ,  A61K8/97 ,  A61K2236/00 ,  A61Q13/00 ,  A61Q17/04 ,  C11B9/00 ,  C11B9/025

    Abstract: Disclosed is a composition containing a Dendropanax morbifera extract. The Dendropanax morbifera extract is used as an active ingredient for relieving stress, blocking UV light, and/or diffusing fragrance. The composition includes essential oil extracted from Dendropanax morbifera leaf, stem or sap, in which the Dendropanax morbifera extract is separated under optimal extraction conditions, which are determined by comparing and evaluating the components and yields of the essential oil, thus ensuring maximum efficacy and various applications of Dendropanax morbifera.

    Abstract translation: 公开了含有Dendropanax morbifera提取物的组合物。 Dendropanax morbifera提取物用作缓解应激，阻挡UV光和/或扩散香料的活性成分。 组合物包括从Dendropanax morbifera叶，茎或汁提取的精油，其中Dendropanax morbifera提取物在最佳提取条件下分离，其通过比较和评估精油的组分和产率来确定，从而确保最大功效和各种 Dendropanax morbifera的应用。

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