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    Forming ultra-shallow junctions
    33.
    发明授权
    Forming ultra-shallow junctions 有权
    形成超浅结

    公开(公告)号：US07456068B2

    公开(公告)日：2008-11-25

    申请号：US11449972

    申请日：2006-06-08

    Applicant: Jack T. Kavalieros ,  Mark Y. Liu ,  Suman Datta

    Inventor： Jack T. Kavalieros ,  Mark Y. Liu ,  Suman Datta

    IPC: H01L21/336 ,  H01L21/4763

    CPC classification number: H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/7851

    Abstract: A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement gate process. In one embodiment, an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.

    Abstract translation: 描述了形成超浅结的方法。 在一个实施例中，利用替代栅极工艺来使栅电极在尖端延伸部分所在的半导体衬底的区域上重叠。 在另一个实施例中，牺牲间隔物与替代浇口工艺结合使用。 在一个实施例中，初始栅极形成的栅极长度小于期望的最终栅极长度，并且随后被具有期望栅极长度的扩展栅极电极替代。

    Capacitor, method of increasing a capacitance area of same, and system containing same
    36.
    发明申请
    Capacitor, method of increasing a capacitance area of same, and system containing same 有权
    电容器，增加电容面积相同的方法，以及包含其的系统

    公开(公告)号：US20080237675A1

    公开(公告)日：2008-10-02

    申请号：US11731543

    申请日：2007-03-29

    Applicant: Brian S. Doyle ,  Roberts S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

    Inventor： Brian S. Doyle ,  Roberts S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

    IPC: H01L27/108 ,  H01L21/20 ,  H01L29/92

    CPC classification number: H01L28/91 ,  H01L27/10852 ,  H01L29/785

    Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

    Abstract translation: 电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。 第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。 第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。 第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。 在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

    Stacked multi-gate transistor design and method of fabrication
    38.
    发明授权
    Stacked multi-gate transistor design and method of fabrication 有权
    堆叠多栅晶体管的设计与制作方法

    公开(公告)号：US07407847B2

    公开(公告)日：2008-08-05

    申请号：US11395860

    申请日：2006-03-31

    Applicant: Brian S Doyle ,  Titash Rakshit ,  Robert S Chau ,  Suman Datta ,  Justin K Brask ,  Uday Shah

    Inventor： Brian S Doyle ,  Titash Rakshit ,  Robert S Chau ,  Suman Datta ,  Justin K Brask ,  Uday Shah

    IPC: H01L21/84

    CPC classification number: H01L29/7853 ,  H01L29/66818

    Abstract: A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a narrow section, each pair being located at a different height of the silicon body. The silicon body is surrounded by a gate material on three sides. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The MBT-FET combines the advantages of a wide fin device and a narrow fin device.

    Abstract translation: 多体厚度（MBT）场效应晶体管（FET）包括形成在衬底上的硅体。 硅体可以包括在宽部分和基底之间的宽的部分和窄的部分。 硅体可以包括多于一对宽的部分和窄的部分，每对位于硅体的不同高度处。 硅体由三面的栅极材料包围。 衬底可以是体硅衬底或绝缘体上硅（SOI）衬底。 MBT-FET结合了宽鳍片器件和窄鳍片器件的优点。

    Strain-inducing semiconductor regions
    40.
    发明申请
    Strain-inducing semiconductor regions 有权
    应变诱导半导体区域

    公开(公告)号：US20080142785A1

    公开(公告)日：2008-06-19

    申请号：US11450745

    申请日：2006-06-09

    Applicant: Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

    Inventor： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC: H01L31/00 ,  H01L29/06

    CPC classification number: H01L29/1033 ,  H01L29/0673 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

    Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

    Abstract translation: 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

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